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Digital Design
Chapter 5.3:
Register-Transfer Level
(RTL) Design
ECE 474a/575a Susan Lysecky
Digital DesignCopyright © 2006 2 of 94
Frank Vahid
RTL Design Examples and Issues
- We’ll use several more examples to
illustrate RTL design
Master processor can read register
from any peripheral
- Each register has unique 4-bit address
- Assume 1 register/periph.
Sets rd=1 , A=address
Appropriate peripheral places register
data on 32-bit D lines
- Periph’s address provided on Faddr inputs (maybe from DIP switches, or another register)
32 4 A
rd D
Per0 Per1 Per
Master processor
Faddr
4
rd D A
Bus interface
Main part
Peripheral
Q
32
to/from processor bus
32 4
ECE 474a/575a Susan Lysecky
Digital DesignCopyright © 2006 3 of 94 Frank Vahid
RTL Example: Bus Interface
- Step 1: Create high-level state machine
State WaitMyAddress
- Output “nothing” (“Z”) on D , store peripheral’s register value Q into local register Q
- Wait until this peripheral’s address is seen ( A=Faddr ) and rd=
State SendData
- Output Q1 onto D , wait for rd=0 (meaning main processor is done reading the D lines)
WaitMyAddress
Inputs: rd (bit); Q (32 bits); A, Faddr (4 bits) Outputs: D (32 bits) Local register: Q1 (32 bits) rd’ rd
SendData
D = “Z” Q1 = Q
(A = Faddr) and rd
(A = Faddr) and rd’
D = Q
ECE 474a/575a Susan Lysecky
Digital DesignCopyright © 2006 4 of 94
Frank Vahid
RTL Example: Bus Interface
W W
D Z Q1 Z Q1 Z
SD W W SD SD W
clk
Inputs
State
Outputs
rd
WaitMyAddress
Inputs: rd (bit); Q (32 bits); A, Faddr (4 bits) Outputs: D (32 bits) Local register: Q1 (32 bits) rd’ rd
SendData
D = “Z” Q1 = Q
(A = Faddr) and rd
(A = Faddr) and rd’
D = Q
ECE 474a/575a Susan Lysecky
Digital DesignCopyright © 2006 5 of 94
Frank Vahid
- Step 2: Create a datapath a) Datapath inputs/outputs b) Instantiate declared registers c) Instantiate datapath components and connections
RTL Example: Bus Interface
ld (^) Q
Faddr Q
4 4 32
A
32
D
a
WaitMyAddress
Inputs: rd (bit); Q (32 bits); A, Faddr (4 bits) Outputs: D (32 bits) Local register: Q1 (32 bits) rd’ rd
SendData
D = “Z” Q1 = Q
(A = Faddr) and rd
(A = Faddr) and rd’
D = Q
- Step 2: Create a datapath a) Datapath inputs/outputs b) Instantiate declared registers c) Instantiate datapath components and connections
Datapath
ECE 474a/575a Susan Lysecky
Digital DesignCopyright © 2006 6 of 94 Frank Vahid
RTL Example: Bus Interface
Datapath
Q1_ld ld (^) Q
Faddr Q
4 4 32
A
A_eq_Faddr (4-bit equality) 32
32
D
D_en
a
WaitMyAddress
Inputs: rd (bit); Q (32 bits); A, Faddr (4 bits) Outputs: D (32 bits) Local register: Q1 (32 bits) rd’ rd
SendData
D = “Z” Q1 = Q
(A = Faddr) and rd
(A = Faddr) and rd’
D = Q
- Step 2: Create a datapath a) Datapath inputs/outputs b) Instantiate declared registers c) Instantiate datapath components and connections
ECE 474a/575a Susan Lysecky
Digital DesignCopyright © 2006 10 of 94 Frank Vahid
RTL Example:
Video Compression – Sum of Absolute Differences
- Want fast sum-of-absolute-differences (SAD) component
When go=1 , sums the differences of element pairs in arrays A and B , outputs that
sum
!(i< 256 )
B
A
go
SAD
sad
256-byte array
256-byte array
integer
ECE 474a/575a Susan Lysecky
Digital DesignCopyright © 2006 11 of 94 Frank Vahid
RTL Example:
Video Compression – Sum of Absolute Differences
- Step 1: Create high-level state machine
S0 - wait for go
S1 - initialize sum and index
S2 - check if done ( i>=256 )
S3 - add difference to sum , increment
index
S4 - done, write to output sad_reg
!(i< 256 )
B
A
go
SAD
sad
Inputs: A, B (256 byte memory); go (bit) Outputs: sad (32 bits) Local registers: sum, sad_reg (32 bits); i (9 bits)
S0 !go
go
S
sum = 0 i = 0
S
sum=sum+abs(A[i]-B[i]) i=i+
S4 sad_ reg = sum
S
i<
(i<256)’
a
ECE 474a/575a Susan Lysecky
Digital DesignCopyright © 2006 12 of 94 Frank Vahid
RTL Example:
Video Compression – Sum of Absolute Differences
Inputs: A, B (256 byte memory); go (bit) Outputs: sad (32 bits) Local registers: sum, sad_reg (32 bits); i (9 bits)
S0 !go go S1 sum = 0i = 0
S3 sum=sum+abs(A[i]-B[i])i=i+
S4 sad_ reg=sum
S
i<
(i<256)’
i_lt_
i_inc
i_clr
sum_ld
sum_clr
sad_reg_ld
Datapath
sum
sad_reg
sad
AB_addr A_data B_data
i –
abs
ECE 474a/575a Susan Lysecky
Digital DesignCopyright © 2006 13 of 94
Frank Vahid
RTL Example:
Video Compression – Sum of Absolute Differences
- Step 3: Connect to controller
- Step 4: Replace high-level state machine by FSM
i_lt_
i_inc
i_clr
sum_ld
sum_clr
sad_reg_ld
Datapath
sum
sad_reg
sad
AB_addr A_data B_data
i –
abs
S0 !go go
S
sum = 0 i = 0
S3 sum=sum+abs(A[i]-B[i]) i=i+
S4 sad_ reg=sum
S
i<
(i<256)’
Controller
go AB_ rd
sum_clr= i_clr=
i_lt_
i_inc=
i_lt_256’
sum_ld=1; AB_rd=
sad_reg_ld=
ECE 474a/575a Susan Lysecky
Digital DesignCopyright © 2006 14 of 94
Frank Vahid
RTL Example:
Video Compression – Sum of Absolute Differences
- Comparing software and custom
circuit SAD
Circuit: Two states ( S2 & S3 ) for each
i , 256 i ’sÆ 512 clock cycles
Software: Loop ( for i = 1 to 256 ), but
for each i , must move memory to local
registers, subtract, compute absolute
value, add to sum, increment i – say
about 6 cycles per array item Æ 256*
= 1536 cycles
Circuit is about 3 times (300%) faster
Later, we’ll see how to build SAD
circuit that is even faster
!(i< 256 )
!(i< 256 )(i_lt_ 256 )
S3 sum=sum+abs(A[i]-B[i])
i=i+
S
i<
(i<256)’
ECE 474a/575a Susan Lysecky
Digital DesignCopyright © 2006 15 of 94 Frank Vahid
RTL Design Pitfalls and Good Practice
- Common pitfall: Assuming register
is update in the state it’s written
Final value of Q?
Final state?
Answers may surprise you
- Value of Q unknown
- Final state is C , not D
Why?
- State A : R=99 and Q=R happen simultaneously
- State B : R not updated with R+ until next clock cycle, simultaneously with state register being updated
A B
C
D
R>=
R<
R=99 R=R+
Q=R
A
B
C
R<
clk
R
Q
(a)
(b)
Local registers: R, Q (8 bits)
ECE 474a/575a Susan Lysecky
Digital DesignCopyright © 2006 19 of 94
Frank Vahid
Control vs. Data Dominated RTL Design
- Designs often categorized as control-dominated or data-dominated
Control-dominated design – Controller contains most of the complexity
Data-dominated design – Datapath contains most of the complexity
General, descriptive terms – no hard rule that separates the two types of designs
Laser-based distance measurer – control dominated
Bus interface, SAD circuit – mix of control and data
Now let’s do a data dominated design
ECE 474a/575a Susan Lysecky
Digital DesignCopyright © 2006 20 of 94
Frank Vahid
Data Dominated RTL Design Example:
FIR Filter
Suppose X is data from a temperature
sensor, and particular input sequence is
180, 180, 181, 240 , 180, 181 (one per clock
cycle)
That 240 is probably wrong!
- Could be electrical noise
Filter should remove such noise in its
output Y
Simple filter: Output average of last N
values
- Small N : less filtering
- Large N : more filtering, but less sharp output
Y
clk
X
digital filter
ECE 474a/575a Susan Lysecky
Digital DesignCopyright © 2006 21 of 94 Frank Vahid
Data Dominated RTL Design Example:
FIR Filter
“Finite Impulse Response”
Simply a configurable weighted sum of
past input values
y(t) = c0x(t) + c1x(t-1) + c2*x(t-2)
- Above known as “3 tap”
- Tens of taps more common
- Very general filter – User sets the constants (c0, c1, c2) to define specific filter
Y
clk
X
digital filter
y(t) = c0x(t) + c1x(t-1) + c2*x(t-2)
- Step 1: Create high-level state machine
But there really is none! Data dominated
indeed.
ECE 474a/575a Susan Lysecky
Digital DesignCopyright © 2006 22 of 94
Frank Vahid
Data Dominated RTL Design Example:
FIR Filter
Begin by creating chain of x(t)
registers to hold past values of X
a
Y
clk
X
digital filter
y(t) = c0x(t) + c1x(t-1) + c2*x(t-2)
xt0 xt1 xt
x(t) x(t-1) x(t-2)
3-tap FIR filter
X
Y
clk
12 12
12
ECE 474a/575a Susan Lysecky
Digital DesignCopyright © 2006 23 of 94
Frank Vahid
Data Dominated RTL Design Example:
FIR Filter
- Step 2: Create datapath (cont.)
Instantiate registers for c0, c1, c
Instantiate multipliers to compute c*x values
xt0 xt1 xt
x(t) x(t-1) x(t-2)
3-tap FIR filter
X
Y
clk
c0 c1 c
∗ ∗ ∗
a
Y
clk
X
digital filter
y(t) = c0x(t) + c1x(t-1) + c2*x(t-2)
ECE 474a/575a Susan Lysecky
Digital DesignCopyright © 2006 24 of 94 Frank Vahid
Data Dominated RTL Design Example:
FIR Filter
- Step 2: Create datapath (cont.)
Instantiate adders
a
xt0 xt1 xt
x(t) x(t-1) x(t-2)
3-tap FIR filter
X
Y
clk
c0 c1 c
∗ ∗ ∗
Y
clk
X
digital filter
y(t) = c0x(t) + c1x(t-1) + c2*x(t-2)
