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ECE 474a/575a Susan Lysecky
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ECE 474A/57A
Computer-Aided Logic Design
Lecture 3
REVIEW - Sequential Logic Design
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ECE 474a/575a Susan Lysecky
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Sequential Circuits
Output based on inputs as well as previous
inputs (state)
Previously learned how to store data which
can store “state” of circuit (Registers)
Two categories of sequential circuits
Synchronous – clock used to control
operation of circuit
Asynchronous – no clock
We’ll focus on synchronous sequential
circuits A sequential circuit that controls Boolean
outputs based on Boolean inputs and a specific time-ordered behavior is often called a controller
Controller
clk
b x
Sequential Circuit Design (Controllers)
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ECE 474a/575a Susan Lysecky
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Outputs: x
Off On
x=0 x=
clk^
clk^
Off On^ Off On^ Off On Off On
cycle 1
Off On Off On
clk cycle 2^ cycle 3^ cycle 4
state
x
Outputs:
State Diagram or Finite-State
Machine (FSM)
A way to describe desired behavior of
sequential circuit
List states, and transitions among
states
Example: Make x toggle (0 to 1, or 1
to 0) every clock cycle
Two states
Off (x=0) On (x=1)
Transition from Off to On, or On to
Off, on rising clock edge
Arrow with no starting state points to
initial state (when circuit first starts)
** clk^ denotes rising edge of the clock
Describing Behavior of Sequential Circuit: FSM
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ECE 474a/575a Susan Lysecky
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Off Off Off Off OffOn1On2 On3Off
clk
State Outputs:
Inputs:
x
b
On1 On2 On
Off
clk ^
clk ^
x=1 x=1 x=
x=
clk ^
b’•clk ^
b•clk ^
Outputs: x
Inputs: b
Laser Timer
When button pressed (b=1), turn laser on (x=1) for 3 clock cycles
Four states
Off state Keep laser turned off While b=0 (b’), we are in a wait state When b=1 and rising clock edge (b • clk^), transition to On1 state On1 state Turns laser on (x=1) On next rising clock edge (clk^) transition to On2 state On2/On3 state Also turns laser on (x=1) Transitions on next rising clock edge
So x=1 for three cycles after button
pressed
FSM Example: Three-Cycles High Laser Timer
Controller x
b
clk
laser
patient
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ECE 474a/575a Susan Lysecky
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Detect if two inputs in a row are
equal to 1
0, 0, 1, 0, … - invalid pattern
0, 1, 1, 0, … - pattern detected
0, 1, 1, 1, … - pattern detected
twice
Can describe as FSM
State A - Wait state looking for
first “1” on input
State B - Looking for second “1”
on input
State C - Detected two “1”s in a
row
Outputs: z
A B
C
clk^ • w
clk^ • w’
z=
z=0 clk^ • w z=
Inputs: w
clk^ • w’
clk^ • w’
clk^ • w
A B A B CABCC
clk
State
Inputs:
Outputs:
w
z
FSM Example: Two Inputs in a Row are One
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Note: Transition with no associated condition, on next clock cycle goes to next state.
Showing rising clock on every transition:
cluttered
Make implicit -- assume every edge has
rising clock, even if not shown
What if we wanted a transitionwithout a
rising edge
We don’t consider such asynchronous
FSMs -- less common, and advanced topic
Only consider synchronous FSMs --
rising edge onevery transition
On1 On2 On
Off
clk^
clk^
x=1 x=1 x=
x=
clk^
b’•clk^
b•clk^
Outputs: x
Inputs: b
On1 On2 On
Off
x=1 x=1 x=
x= b’
b
Outputs: x
Inputs: b
FSM Simplification: Rising Clock Edges Are Implicit
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ECE 474a/575a Susan Lysecky
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State Table
Encoding states
Can’t store word “Off” in state register so we must encode it Ensure every state has a unique encoding We have 4 states, so we need 2 bits to uniquely identify each state
Fill in table the appropriate state
encodings
On1 On2 On
Off
x=1 x=1 x=
x=
b’
b
Inputs Outputs s1 s0 b n1 n0 x
Off^0
On1^0
On2^1
On3^1
00
(^01 10 )
State Table Example: Laser Timer (cont’)
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ECE 474a/575a Susan Lysecky
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State Table
Next state
Based on current state and FSM input what is the next state?
FSM Output
Output depends on current state only (Moore FSM) For each state we are currently in, what is the output?
On1 On2 On
Off
x=1 x=1 x=
x= b’
b
Inputs Outputs s1 s0 b n1 n0 x 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
Off
On
On
On
00
(^01 10 )
State Table Example: Laser Timer (cont’)
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How does choice of flip-flop impact
the state table?
Different ways to store a bit
D flip-flop - Input value determines output value SR flip-flop - Two inputs S (set) and R (reset) that determines output value
We usually use D flip-flop
Simpler
Area not as big a concern
Combinational logic
State register
s1 s
n
n
b x
clk
FSM inputs FSM outputs
S (^) Q’ R Q
SR flip-flop
D Q’ Q
D flip-flop
S = 0, R = 0 then Q = Q S = 0, R = 1 then Q = 0 S = 1, R = 0 then Q = 1 S = 1, R = 1 is invalid
D = 1 then Q = 1 D = 0 then Q = 0
Flip-flop Choice Impacts the State Table
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Create an FSM (state diagram) that describes the desired behavior of the circuit
Step 1: Capture the FSM
Create the standard architecture by using a state register of appropriate width, and combinational logic with inputs being the state register bits and the FSM inputs, and outputs being the next state bits and the FSM outputs
Step 2: Create the architecture
Assign a unique binary number to each state. Each binary number representing a state is know as an encoding. Any encoding will do as long as they are unique.
Step 3: Encode the states
Create a truth table for the combinational logic such that the logic will generate the correct FSM output and next state signals. Ordering the inputs with state bits first make the truth table describe the state behavior, giving us a state table.
Step 4: Create the state table
Implement the Implement the combinational logic using any method. combinational logic
Step 5:
Step Description
(Condensed) Controller Design Process
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Example: Laser Timer
Step 1: Capture the FSM
Already done
Step 2: Create architecture
Customize generic controller architecture
to our system
State Register 2-bit state register (for 4 states) s1, s0 – current state bits n1, n0 – next state bits FSM Input Button signal b FSM Output Laser control x
On1 On2 On
Off
x=1 x=1 x=
x= b’
b
x
clk State register
n
n
Combinational logic
s1 s
b
FSM inputs FSM outputs
Controller Design: Laser Timer
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Step 3: Encode the states
Any encoding with each state unique
will work
Step 4: Create state table
Done this already
On1 On2 On
Off
x=1 x=1 x=
x= b’
b
00
01 10 11
Inputs Outputs s1 s0 b n1 n0 x 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
Off
On
On
On
Controller Design: Laser Timer (Cont’)
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Inputs: x; Outputs: b
On1 On2 On
Off
x=1 x=1 x=
x= b’
b
All our FSMs had initial state
But our sequential circuit designs
did not
Can accomplish using flip-flops with
preset/clear inputs
Shown circuit initializes flip-flops to 01
Designer must ensure reset input is
1 during power up of circuit
By electronic circuit design
D Q
P C
D (^) Q
State register clk
reset
s1 s
n
n
b x Combinational logic
Initial State of a Controller
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Representations of Finite State Machines
Different ways to represent same
functionality
Graphical
State Table
Formal
Able to convert among different
representations
On1 On2 On
Off
x=1 x=1 x=
x= b’
b
00
(^01 10 )
0 0 0 1
0 0 1 0 1 0
1 1 1 1 1 1
1 1 0 0 0 0
1 1
Inputs Outputs s1 s0 b n1 n0 x 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
Off
On
On
On
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FSM defined by quintuple
M = (X, Y, S, δ, λ, so )
X is the input alphabet
Y is the output alphabet
S is a finite set of states
δ is the transition function, δ: X x S→S
Given and input and state, what is the
next state
λ is the output funciton, λ: S → Y
Mealy FSM, λ: X x S → Y
so is the initial state
On1 On2 On
Off
x=1 x=1 x=
x=
b’
b
Outputs: x
Inputs: b
FSM Formal Definition
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Formally specify the Laser Timer FSM
M = (X, Y, S, δ, λ, so )
On1 On2 On
Off
x=1 x=1 x=
x= b’
b
Outputs: x
Inputs: b
FSM Formal Definition – Example 1
LaserTimer = (X, Y, S, δ, λ, qo), where
X is the input alphabet
X = {0, 1}
Y = {0, 1}
Y is the output alphabet
S = {Off, On1, On2, On3}
S is a finite set of states
δ(Off, 0) = Off, δ(Off, 1) = On δ(On1, 0) = On2, δ(On1, 1) = On δ(On2, 0) = On3, δ(On2, 1) =On δ(On3, 0) = Off, δ(On3, 1) = Off δ^ is the transition function,^ δ: X x S→S Given and input and state, what is the next state λ(Off) = 0, λ(On1) = 1, λ(On2) = 1, λ(On3) = 1 λ is the output funciton, λ: S → Y so = Off
s (^) o is the initial state
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FSM Formal Definition - Example 2
Given formal specification of ThreeOnes
FSM convert to graphical representation
x=0 x=0 x=
x=
One Two Three
Zero
ThreeOnes = (X, Y, S, δ, λ, qo), where
X = {0, 1}
Y = {0, 1}
S = {Zero, One, Two, Three}
δ(Zero, 0) = Zero, δ(Zero, 1) = One δ(One, 0) = Zero, δ(One, 1) = Two δ(Two, 0) = Zero, δ(Two, 1) = Three δ(Three, 0) = Zero, δ(Three, 1) = Three
λ(Zero) = 0, λ(One) = 0, λ(Two) = 0, λ(Three) = 1
q (^) o = Zero
Inputs: a Output: x
a’
a
a’
a
a
a’ a
a’
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Previously associated output with
current state
Moore FSM
Another type associates output with
both the state and the FSM input
(transitions)
Mealy FSM
Example: Soda dispenser
Input
enough - indicates when sufficient
money deposited
Output
d - releases a soda
clear - zeros device counting money
deposited
Moore FSM
Inputs: enough (bit) Outputs: d, clear (bit)
Wait
Disp
Init (^) enough’
enough
d= clear=
d=
Mealy FSM
Inputs: enough (bit) Outputs: d, clear (bit)
Init Wait
enough/d=1 enough’
/d=0, clear=
Outputs not explicitly assigned on a transition are implicitly assigned a 0. Assignment to 0 still listed if it is key to the FSM’s behavior
Mealy vs. Moore FSM
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Inputs: b; Outputs: s1, s0, p
Time
Alarm
Date
Stpwch
b’/s1s0=00, p= b/s1s0=00, p=
b/s1s0=01, p=
b/s1s0=10, p=
b/s1s0=11, p=
b’/s1s0=01, p=
b’/s1s0=10, p=
b’/s1s0=11, p=
Inputs: b; Outputs: s1, s0, p
Time
S
Alarm
b
b
b
b
s1s0=00, p= s1s0=00, p=
s1s0=01, p=
s1s0=01, p=
s1s0=10, p= s1s0=10, p=
s1s0=11, p=
s1s0=11, p=
S
Date
S
Stpwch
S
b’
b’
b’
b’
Mealy
Moore
A: Mealy on left, Moore on
right
- Mealy outputs on arcs, meaning outputs are function of state AND INPUTS
- Moore outputs in states, meaning outputs are function of state only
Q: Which is Moore, and
which is Mealy?
Which One is Which: Moore vs. Mealy
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Inputs: b; Outputs: s1, s0, p
Time
Alarm
Date
Stpwch
b’/s1s0=00, p= b/s1s0=00, p=
b/s1s0=01, p=
b/s1s0=10, p=
b/s1s0=11, p=
b’/s1s0=01, p=
b’/s1s0=10, p=
b’/s1s0=11, p=
Mealy
Beeping Wristwatch
Button b
Sequences mux select liness1s0 through
00, 01, 10, and 11 Each value displays different internal register Each unique button press should cause 1-
cycle beep, withp = 1 causing the beep
Must wait for button to be released (b’)
and pushed again (b) before sequencing
Mealy pulsesp on arc
Benefit: We’ll see it requires less states
than Moore FSM
Tradeoff: Mealy FSM’s pulse onp may not
last one full cycle
Mealy FSM Example: Beeping Wristwatch
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Inputs: b; Outputs: s1, s0, p
Time
S
Alarm
b
b
b
b
s1s0=00, p=
s1s0=00, p=
s1s0=01, p= s1s0=01, p=
s1s0=10, p=
s1s0=10, p=
s1s0=11, p=
s1s0=11, p=
S
Date
S
Stpwch
S
b’
b’
b’
b’
Moore
Beeping Wristwatch using Moore
FSM
Moore FSM needs separate state to
pulsep
Benefit: pulse on p lasts one full
clock cycle
Tradeoff: greater number of states
required
Moore FSM Example: Beeping Wristwatch
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Implementing a Mealy FSM
Same steps as a Moore FSM
Capture the FSM
Create the architecture
Encode the states
Create the state table
Derive equations for each output,
implement the combinational
logic
Key difference from Moore
FSM output are based on state
and FSM inputs
May have different value in same
state, depending on input values
Inputs: enough (bit) Outputs: d, clear (bit)
Init Wait
enough/d=1 enough’
/d=0, clear=
Implementing a Mealy FSM
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Capture the FSM
Done!
Create the architecture
Inputs – enough
Outputs – d, clear
State register – 2 states, 1-bit
Inputs: enough (bit) Outputs: d, clear (bit)
Init Wait enough’ enough/d=
/d=0, clear=
d
clk State register
Combinational clear logic
s
enough
FSM inputs FSM outputs n
Implementing a Mealy FSM Example 1
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s0 enough n0 d clear
Encode the states
Use minimum-width binary
encoding
Create the state table
This is where it differs from a
Moore implementation
FSM output are based on
state and FSM inputs
May have different value in
same state, depending on
input values
Inputs: enough (bit) Outputs: d, clear (bit)
Init Wait enough’ enough/d=
/d=0, clear=
(^0 )
Init
Wait
Inputs Outputs
Implementing a Mealy FSM Example 1 (cont’)
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Converting a Mealy to a Moore FSM
b’
S1 (^) a=
a=
What happens when bc’? go to state S output a = 1
go to state S output a = 1
State S What happens when b’?
S
S
b’ / a=
bc’ / a=1 bc / a=
What happens when bc? go to S output a = 0
State S0 already associated with a = 1!
Replicate state, new state’s output is a = 0
S
bc’
S0B
bc
a=
A
Converting a Mealy to a Moore FSMs
Template 2
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Convert the following Mealy FSM to a Moore FSM
in wait state output 00
when start signal received, counts 01, 10, 11
waits for start signal before repeating count
What does FSM do?
S1 S
S
/ ab=
/ ab=
start’ / ab = 00
Outputs: a,b
Inputs: start
start / ab = 01
Converting a Mealy to a Moore FSMs Example
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Convert the following Mealy FSM to a Moore FSM
go to state S output ab = 00
State S What happens when start’?
S1 S
S
/ ab=
/ ab=
start’ / ab = 00
Outputs: a,b
Inputs: start
start / ab = 01
S0 (^) start’ ab = 00
S
start
ab = 01
go to state S output ab = 01
What happens when start?
Converting a Mealy to a Moore FSMs Example
(cont’)
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Convert the following Mealy FSM to a Moore FSM
State S Don’t care what input start value is
S1 S
S
/ ab=
/ ab=
start’ / ab = 00
Outputs: a,b
Inputs: start
start / ab = 01
go to state S output ab = 10
S ab=
S
S0 (^) start’
start
ab = 00
ab = 01
Converting a Mealy to a Moore FSMs Example
(cont’)
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Convert the following Mealy FSM to a Moore FSM
go to state S output ab = 11
State S Don’t care what input start value is
S1 S
S
/ ab=
/ ab=
start’ / ab = 00
Outputs: a,b
Inputs: start
start / ab = 01
S1 S
S
ab=
start’
start
ab = 00
ab = 01
a
ab=
S0b
State S0 already associated with ab = 00!
Replicate state, new state’s output is a = 11
Converting a Mealy to a Moore FSMs Example
(cont’)
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Convert the following Mealy FSM to a Moore FSM
State S0b What happens when start’?
S1 S
S
/ ab=
/ ab=
start’ / ab = 00
Outputs: a,b
Inputs: start
start / ab = 01
S1 S
S ab=
ab=
start’
start
S0b ab = 00
ab = 01
a
go to state S output ab = 00 (this is S0a)
start’
start
go to state S output ab = 01
What happens when start?
Converting a Mealy to a Moore FSMs Example
(cont’)
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Converting the following Moore FSM to a Mealy FSM
go to state S output a = 1
State S We don’t care what input value b is equal to
b’
S
a=
S
b
S
a=
a=
b’ (^) b
b’ / a = 1
S
S
b / a = 1
S
b’ / a = 1 b / a = 0
/ a = 1
Converting a Moore to a Mealy FSMs Example
(cont’)
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Inputs: b; Outputs: s1, s0, p
Time
Alarm
Date
Stpwch
b’/p=
b/p=
s1s0=
s1s0= b/p=
b/p=
s1s0=
b/p=
s1s0=
b’/p=
b’/p=
b’/p=
Combined
Moore/Mealy
FSM for beeping
wristwatch
example
Final note on Mealy/Moore
May be combined in same FSM
Mealy and Moore FSMs Can be Combined
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Summary
FSM Representations
Graphical – State Diagram (states & transitions)
Text - State Table
Formal Model, M = (X, Y, S, δ, λ, so )
Controller design process
FSM specification to hardware
Moore vs. Mealy FSM
Specification
Timing
Conversion between Moore and Mealy
