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ECE 474a/575a Susan Lysecky
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ECE 474A/57A
Computer-Aided Logic Design
Lecture 4
Sequential Logic Design
Digital Design Copyright © 2006 Frank Vahid
ECE 474a/575a Susan Lysecky
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Sequential Circuits
Output based on inputs as well as previous
inputs (state)
Previously learned how to store data which
can store “state” of circuit (Registers)
Two categories of sequential circuits
Synchronous – clock used to control
operation of circuit
Asynchronous – no clock
We’ll focus on synchronous sequential
circuits A sequential circuit that controls Boolean
outputs based on Boolean inputs and a specific time-ordered behavior is often called a controller
Controller
clk
b x
Sequential Circuit Design (Controllers)
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ECE 474a/575a Susan Lysecky
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Controller x
b
clk
laser
patient
Want sequential circuit with
particular behavior over time
Example: Laser timer
When button pressed (b=1),
output x=1 (turn laser on) for 3
clock cycles
How? Let’s try three flip-flops
b=1 gets stored in first D flip-flop
Then 2nd flip-flop on next cycle,
then 3rd flip-flop on next
OR the three flip-flop outputs, so
x should be 1 for three cycles
D Q D Q D Q
clk
b
x
Example System: Laser Timer Controller
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ECE 474a/575a Susan Lysecky
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Does this work correctly?
What happens if we press the button
again while x=1?
Laser remains on for another 3 clock cycles
Trial and error is not a good design
method
Will we be able to “guess” a circuit that
works for other desired behavior?
Pulsing an output for 1 cycle every 10 cycles Detecting the sequence 1, 3, 5 in binary on a 3-bit input
Circuit built by guessing may have
undesired behavior
Laser timer example of multiple button presses
D Q1 D Q2 D Q
clk
b
x
b Q1 Q2 Q3 x
time0 1 0 0 0 0
time1 0 1 0 0 1
time2 1 0 1 0 1
time3 0 1 0 1 1
time4 0 0 1 0 1
time5 0 0 0 1 1
time6 0 0 0 0 0
Does the Laser Timer Controller Really Work?
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ECE 474a/575a Susan Lysecky
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Designing sequence circuits
Need a formal way to describe
desired circuit behavior
Combinational Circuits have
Boolean equations or truth table
Well-defined process to convert
that behavior to a circuit
x1 x2 F 0 1 0 1 0 1 0 1
0 0 1 1 0 0 1 1
0 0 0 0 1 1 1 1
x 0 0 0 1 1 1 1 0
F = x1x3’ + x1x2’ + x1’x2x
F
x
x x
x x
x
x
Need a Better Way to Design Sequential Circuits
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ECE 474a/575a Susan Lysecky
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Outputs: x
Off On
x=0 x=
clk^
clk^
Off On^ Off On^ Off On Off On
cycle 1
Off On Off On
clk cycle 2^ cycle 3^ cycle 4
state
x
Outputs:
State Diagram or Finite-State
Machine (FSM)
A way to describe desired behavior of
sequential circuit
List states, and transitions among
states
Example: Make x toggle (0 to 1, or 1
to 0) every clock cycle
Two states
Off (x=0) On (x=1)
Transition from Off to On, or On to
Off, on rising clock edge
Arrow with no starting state points to
initial state (when circuit first starts)
** clk^ denotes rising edge of the clock
Describing Behavior of Sequential Circuit: FSM
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ECE 474a/575a Susan Lysecky
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Many new car keys include tiny
computer chip
When car starts, car’s computer
(under engine hood) requests
identifier from key
Key transmits identifier
If not, computer shuts off car
FSM
Wait until computer requests ID
(a=1)
Transmit ID (in this case, 1101)
K1 K2 K3 K
r=1 r=1 r=0 r=
Wait
r=
a a’
Outputs: r
Inputs: a
FSM Example: Secure Car Key
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ECE 474a/575a Susan Lysecky
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Wait Wait K1 K2 K3 K4 Wait Wait Outputs
State
r
Q: Determine states and r value for given input waveform:
clk Inputs a
clk Inputs a
Nice feature of FSM
Can evaluate output behavior for
different input sequence
Timing diagrams show states and
output values for different input
waveforms
K1 K2 K3 K
r=1 r=1 r=0 r=
Wait
r=
a a’
Outputs: r
Inputs: a
Wait Wait K1 K2 K3 K4 Wait Output
State
r
K
FSM Example: Secure Car Key (cont.)
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ECE 474a/575a Susan Lysecky
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Start
Red Green Blue
s
r g b a
Door lock
u
Code Detector
Unlock door only when buttons
pressed in sequence:
start, then red, blue, green, red
Input
Each button indicates when pressed
s, r, g, b
Extra input to indicate some colored
button pressed
a
Output
Door unlocked when u = 1
FSM Example: Code Detector Description
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ECE 474a/575a Susan Lysecky
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Q: Can you trick this FSM to open the door, without knowing the code?
A: Yes, hold all buttons simultaneously
Red
ar
u=
Inputs: s,r,g,b,a; Outputs: u
FSM to detect S, R, B, G, R
Wait for Start (s=1) Once start button pressed check for correct sequence If Red pressed, go to “Red1” Then, if Blue pressed, go to “Blue” Then, if Green pressed, go to “Green” Then, if Red pressed, go to “Red2” Correct sequence detected Open the door (u=1) Return to Wait Wrong button at any step, return to “Wait”, without opening door
Start Red Green Blue
s r g b a
Doorlock
u DetectorCode
ar’ ab’ ag’ ar’
Start a’ u=
s
Blue
ab
a’ u=
a’
Red u=
ar
Green
ag
a’ u=
Wait u=0 s
FSM Example: Code Detector FSM
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Note: small problem still remains; we’ll discuss later
Update transition conditions
Detect if wrong button pressed, returns to “Wait”
Red
ar
u=
Inputs: s,r,g,b,a; Outputs: u
Start u=
s
Blue
ab
a’ u=
a’
Red
u=
ar
Green
ag
a’ u=
Wait u=0 ar ’ ab ’ ag ’ ar ’
a’
s’
Improved FSM for Code Detector
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ECE 474a/575a Susan Lysecky
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FSM or state diagram
Graphical representation
Formal method to describe sequential
circuits
State Table
Textual Representation
How do we implement a sequential
circuit?
Standard Controller architecture
Need to store state State register (encoded state) Need to determine next state Current state and external input to combinational logic Need to determine output Current state input to combinational logic
On1 On2 On
Off
x=1 x=1 x=
x= b’
b
x
clk State register
n
n
Combinational logic
s1 s
b
FSM inputs FSM outputs
Controller architecture for laser timer example
Graphical and Textual Sequential Circuit
Descriptions
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ECE 474a/575a Susan Lysecky
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State Table
Next state
Based on current state and FSM input what is the next state?
FSM Output
Output depends on current state only (Moore FSM) For each state we are currently in, what is the output?
On1 On2 On
Off
x=1 x=1 x=
x=
b’
b
Inputs Outputs s1 s0 b n1 n0 x 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
Off
On
On
On
00
(^01 10 )
State Table Example: Laser Timer (cont’)
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ECE 474a/575a Susan Lysecky
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How does choice of flip-flop impact
the state table?
Different ways to store a bit
D flip-flop - Input value determines output value SR flip-flop - Two inputs S (set) and R (reset) that determines output value
We only consider D flip-flop
Combinational logic
State register
s1 s
n
n
b x
clk
FSM inputs FSM outputs
S Q’ R Q
SR flip-flop
D Q’ Q
D flip-flop
S = 0, R = 0 then Q = Q S = 0, R = 1 then Q = 0 S = 1, R = 0 then Q = 1 S = 1, R = 1 is invalid
D = 1 then Q = 1 D = 0 then Q = 0
Flip-flop Choice Impacts the State Table
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ECE 474a/575a Susan Lysecky
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Given FSM, create corresponding
state table
Two consecutive inputs (w) are
equal to 1
Steps to create a state table
Encode states
Three states, need 2-bits for unique encoding
Determine inputs/outputs of FSM
Don’t forget state!
Fill in all possible input values
Current state and FSM inputs
Fill in Next state
Given current state and FSM input, where do we go?
Fill in FSM Output
00 01
10
d d d d
d d
Inputs Outputs s1 s0 w n1 n0 z 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
A
B
C
Unused
Outputs: z
A B
C
w
w’
z=
z=0 w z=
Inputs: w
w’ w’
w
State Table Example: Secure Car Key
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ECE 474a/575a Susan Lysecky
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Create an FSM (state diagram) that describes the desired behavior of the circuit
Step 1: Capture the FSM
Create the standard architecture by using a state register of appropriate width, and combinational logic with inputs being the state register bits and the FSM inputs, and outputs being the next state bits and the FSM outputs
Step 2: Create the architecture
Assign a unique binary number to each state. Each binary number representing a state is know as an encoding. Any encoding will do as long as they are unique.
Step 3: Encode the states
Create a truth table for the combinational logic such that the logic will generate the correct FSM output and next state signals. Ordering the inputs with state bits first make the truth table describe the state behavior, giving us a state table.
Step 4: Create the state table
Implement the Implement the combinational logic using any method. combinational logic
Step 5:
Step Description
(Condensed) Controller Design Process
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ECE 474a/575a Susan Lysecky
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Example: Laser Timer
Step 1: Capture the FSM
Already done
Step 2: Create architecture
Customize generic controller architecture
to our system
State Register 2-bit state register (for 4 states) s1, s0 – current state bits n1, n0 – next state bits FSM Input Button signal b FSM Output Laser control x
On1 On2 On
Off
x=1 x=1 x=
x= b’
b
x
clk State register
n
n
Combinational logic
s1 s
b
FSM inputs FSM outputs
Controller Design: Laser Timer
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ECE 474a/575a Susan Lysecky
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Step 3: Encode the states
Any encoding with each state unique
will work
Step 4: Create state table
Done this already
On1 On2 On
Off
x=1 x=1 x=
x= b’
b
00
01 10 11
Inputs Outputs s1 s0 b n1 n0 x 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
Off
On
On
On
Controller Design: Laser Timer (Cont’)
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ECE 474a/575a Susan Lysecky
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a + a’b = (a • 1) + a’b // a • 1 = a = a • (1+b) + a’b // b + 1 = 1 = a + ab + a’b = a + (a+a’)b = a + b
Fails! Might not be 1 (i.e., a=0, b=0)
a • a’b = (a • a’) • b = 0 • b = 0
OK!
Verify FSM Transition properties using
Boolean algebra
Only one condition true
AND ofeach condition pair for
transitions leaving a state
Should equal 0, proves pair can never
simultaneously be true
1 AND 1 = 1
1 AND 0 = 0
At least one condition true
OR ofall conditions of transitions
leaving a state
Should equal 1 , proves at least one
condition must be true
At least one true condition
Only one true condition
a
a’b
Verifying Correct Transition Properties
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ECE 474a/575a Susan Lysecky
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Fails! Means that two of Start’s transitions could be true
Recall code detector FSM
We “fixed” a problem with the transition
conditions
Do the transitions obey the two required
transition properties?
Consider transitions of stateStart
“Only one true” property
AND each condition pair, should be 0
3 outbound transitions – look at each pair
ar • a’ = (a • a’) • r = 0 • r = 0
a’ • a(r’ + b + g) = (a’ • a) • (r’ + b + g) = 0 • (r’ + b + g) = 0
ar • a(r’ + b + g) = (a • a) • r • (r’ + b + g) = a • r • (r’ + b + g) = arr’ + arb + arg = 0 + arb + arg = arb + arg = ar (b+g)
Wait
Start
Red1 Blue Green Red
s’
a’
a’
ab ag^ ar a’ a’ u=
u=0 ar
u=0 (^) s
u=0 u=0 u=
Evidence that Pitfall is Common
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ECE 474a/575a Susan Lysecky
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What happened?
We want to go from Start to
Red1 if the red button pressed
ar
We underspecified transition
No other buttons should be pressed - arb’g’
Transition should also be
updated for
State Red1’s ab to abr’g’
State Blue’s ag to agr’b’
State Green’s ar to arb’g’
Wait
Start
Red1 Blue Green Red
s’
a’
a’
ab ag^ ar a’ a’ u=
u=0 (^) ar
u= s
u=0 u=0 u=
How Do We Fix It?
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ECE 474a/575a Susan Lysecky
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FSM Outputs
Assume unassigned output
implicitly assigned 0
Clk signal in sequential circuits
Assume unconnected clock
inputs connected to same
external clock
a= b= c=
a= b= c=
b=1 c=
clk a a
Further Simplifying Notations
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Inputs: x; Outputs: b
On1 On2 On
Off
x=1 x=1 x=
x=
b’
b
All our FSMs had initial state
But our sequential circuit designs
did not
Can accomplish using flip-flops with
preset/clear inputs
Shown circuit initializes flip-flops to 01
Designer must ensure reset input is
1 during power up of circuit
By electronic circuit design
D Q
P C
D Q
State register clk
reset
s1 s
n
n
b x Combinational logic
Initial State of a Controller
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Representations of Finite State Machines
Different ways to represent same
functionality
Graphical
State Table
Formal
Able to convert among different
representations
On1 On2 On
Off
x=1 x=1 x=
x= b’
b
00
01 10 11
0 0 0 1
0 0 1 0 1 0
1 1 1 1 1 1
1 1 0 0 0 0
1 1
Inputs Outputs s1 s0 b n1 n0 x 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
Off
On
On
On
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Previously associated output with
current state
Moore FSM
Another type associates output with
both the state and the FSM input
(transitions)
Mealy FSM
Example: Soda dispenser
Input
enough - indicates when sufficient
money deposited
Output
d - releases a soda
clear - zeros device counting money
deposited
Moore FSM
Inputs: enough (bit) Outputs: d, clear (bit)
Wait
Disp
Init enough’
enough
d= clear=
d=
Mealy FSM
Inputs: enough (bit) Outputs: d, clear (bit)
Init Wait enough’ enough/d=
/d=0, clear=
Outputs not explicitly assigned on a transition are implicitly assigned a 0. Assignment to 0 still listed if it is key to the FSM’s behavior
Mealy vs. Moore FSM
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Why does the timing change?
More detailed view of FSM implementation architecture
clk
I O
State register
Combinational Logic
S
N
clk
I
O
State register
Next State Logic
S
N
FSM Output Logic
Moore FSM
Next state logic – function of present state and FSM inputs
Output logic - function of present state only
clk
I
O
State register
Next State Logic
S
N
FSM Output Logic
Mealy FSM
Next state logic – function of present state and FSM inputs
Output logic - function of present state and FSM inputs
Moore vs. Mealy FSM - Architecture
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Moore FSM
Output logic is combinational – output changes when input changes
Only input is state
clk
I
O
State register
Next State Logic
S
N
FSM Output Logic
clk
Inputs: enough State:
Outputs: clear d
I W W DI
Output changes only on rising clock edge Output remains same (at least) until next clock cycle -- minimally high/low for 1 clock cycle
Moore FSM Output Condition
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Mealy FSM
Again output logic is combinational – output changes when input changes
Input is both state and FSM input I
clk
I
O
State register
Next State Logic
S
N
FSM Output Logic
clk
Inputs: enough State:
Outputs: clear d
I W WI
Output can change on rising clock edge or when FSM input changes Output can change mid-cycle if input changes, output may not stay the same for an entire clock cycle
Mealy FSM Output Condition
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Inputs: b; Outputs: s1, s0, p
Time
Alarm
Date
Stpwch
b’/s1s0=00, p= b/s1s0=00, p=
b/s1s0=01, p=
b/s1s0=10, p=
b/s1s0=11, p=
b’/s1s0=01, p=
b’/s1s0=10, p=
b’/s1s0=11, p=
Inputs: b; Outputs: s1, s0, p
Time
S
Alarm
b
b
b
b
s1s0=00, p=
s1s0=00, p=
s1s0=01, p= s1s0=01, p=
s1s0=10, p=
s1s0=10, p=
s1s0=11, p=
s1s0=11, p=
S
Date
S
Stpwch
S
b’
b’
b’
b’
Mealy
Moore
A: Mealy on left, Moore on
right
- Mealy outputs on arcs, meaning outputs are function of state AND INPUTS
- Moore outputs in states, meaning outputs are function of state only
Q: Which is Moore, and
which is Mealy?
Which One is Which: Moore vs. Mealy
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Inputs: b; Outputs: s1, s0, p
Time
Alarm
Date
Stpwch
b’/s1s0=00, p= b/s1s0=00, p=
b/s1s0=01, p=
b/s1s0=10, p=
b/s1s0=11, p=
b’/s1s0=01, p=
b’/s1s0=10, p=
b’/s1s0=11, p=
Mealy
Beeping Wristwatch
Button b
Sequences mux select liness1s0 through
00, 01, 10, and 11 Each value displays different internal register Each unique button press should cause 1-
cycle beep, withp = 1 causing the beep
Must wait for button to be released (b’)
and pushed again (b) before sequencing
Mealy pulsesp on arc
Benefit: We’ll see it requires less states
than Moore FSM
Tradeoff: Mealy FSM’s pulse onp may not
last one full cycle
Mealy FSM Example: Beeping Wristwatch
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Implement as a Mealy FSM
Control signals associated with on
transitions
State A
w = 0, stay put w = 1, start swap with R3 = R R2out = 1, R3in = 1
State B
w = 0/1, set R2 = R R1out = 1, R2in = 1
State C
w = 0/1, set R1 = R R3out = 1, R1in = 1
State D
w = 0/1, indicate we are finished Done = 1
Inputs: w Outputs: R1out , R1 in, R2out , R2in, R3out , R3 in, Done
A
B
C
D
w’
/ R1out = 1, R2 (^) in = 1
/ R3out = 1, R1 (^) in = 1
/ Done = 1
w / R2out = 1, R3in = 1
Mealy FSM: Register Swap
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Implementing a Mealy FSM
Same steps as a Moore FSM
Capture the FSM
Create the architecture
Encode the states
Create the state table
Derive equations for each output,
implement the combinational
logic
Key difference from Moore
FSM output are based on state
and FSM inputs
May have different value in same
state, depending on input values
Inputs: enough (bit) Outputs: d, clear (bit)
Init Wait enough’ enough/d=
/d=0, clear=
Implementing a Mealy FSM
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Capture the FSM
Done!
Create the architecture
Inputs – enough
Outputs – d, clear
State register – 2 states, 1-bit
Inputs: enough (bit) Outputs: d, clear (bit)
Init Wait enough’ enough/d=
/d=0, clear=
d
clk State register
Combinational clear logic
s
enough
FSM inputs FSM outputs n
Implementing a Mealy FSM Example 1
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s0 enough n0 d clear
Encode the states
Use minimum-width binary
encoding
Create the state table
This is where it differs from a
Moore implementation
FSM output are based on
state and FSM inputs
May have different value in
same state, depending on
input values
Inputs: enough (bit) Outputs: d, clear (bit)
Init Wait
enough/d=1 enough’
/d=0, clear=
0 1
Init
Wait
Inputs Outputs
Implementing a Mealy FSM Example 1 (cont’)
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Implement the combinational
logic
n0 = s0’ + enough’
d = s0•enough
clear = s
s0 enough n0 d clear Init
Wait
Inputs Outputs
d
clk State register
clear
s
enough
FSM inputs n0 FSM outputs
Implementing a Mealy FSM Example 1 (cont’)
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Given a Mealy FSM we can convert to a Moore FSM
Given a Moore FSM we can covert to a Mealy FSM
Inputs: w Outputs: R1out , R1 (^) in, R2out , R2 (^) in, R3out , R3in, Done
A
B
C
D
w’
R1out = 1 R2in = 1
R3out = 1 R1in = 1
E Done = 1
w wR2out = 1 R3in = 1
Inputs: w Outputs: R1out , R1 (^) in, R2out , R2in, R3out , R3 (^) in, Done
A
B
C
D
w’
/ R1out = 1, R2 (^) in = 1
/ R3out = 1, R1 (^) in = 1
/ Done = 1
w / R2out = 1, R3in = 1
Converting Between Mealy and Moore FSMs
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Convert the following Mealy FSM to a Moore FSM
go to state S output ab = 00
State S What happens when start’?
S1 S
S
/ ab=
/ ab=
start’ / ab = 00
Outputs: a,b
Inputs: start
start / ab = 01
S0 (^) start’ ab = 00
S
start
ab = 01
go to state S output ab = 01
What happens when start?
Converting a Mealy to a Moore FSMs Example
(cont’)
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Convert the following Mealy FSM to a Moore FSM
State S Don’t care what input start value is
S1 S
S
/ ab=
/ ab=
start’ / ab = 00
Outputs: a,b
Inputs: start
start / ab = 01
go to state S output ab = 10
S ab=
S
S0 start’
start
ab = 00
ab = 01
Converting a Mealy to a Moore FSMs Example
(cont’)
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Convert the following Mealy FSM to a Moore FSM
go to state S output ab = 11
State S Don’t care what input start value is
S1 S
S
/ ab=
/ ab=
start’ / ab = 00
Outputs: a,b
Inputs: start
start / ab = 01
S1 S
S
ab=
start’
start
ab = 00
ab = 01
a ab=
S0b
State S0 already associated with ab = 00!
Replicate state, new state’s output is a = 11
Converting a Mealy to a Moore FSMs Example
(cont’)
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Convert the following Mealy FSM to a Moore FSM
State S0b What happens when start’?
S1 S
S
/ ab=
/ ab=
start’ / ab = 00
Outputs: a,b
Inputs: start
start / ab = 01
S1 S
S ab=
ab=
start’
start
S0b ab = 00
ab = 01
a
go to state S output ab = 00 (this is S0a)
start’
start
go to state S output ab = 01
What happens when start?
Converting a Mealy to a Moore FSMs Example
(cont’)
Digital Design Copyright © 2006 Frank Vahid
ECE 474a/575a Susan Lysecky
59 of 64
Converting a Moore to a Mealy FSM
Time
b’ / a=
Alarm
b / a=
Time
b’
Alarm
b
a=
a=
What happens when b = 1? go to state alarm state alarm outputs a = 0 (make this output associated with the transition
go to state time state time outputs a = 1 (make this output associated with the transition)
State Time What happens when b = 0?
Converting a Moore to a Mealy FSMs
Template 1
Digital Design Copyright © 2006 Frank Vahid
ECE 474a/575a Susan Lysecky
60 of 64
Converting the following Moore FSM to a Mealy FSM
What happens when b? go to state S output a = 1
go to state S output a = 1
State S What happens when b’?
b’
S
a=
S
b
S
a=
a=
b’ b S
b / a = 1
b’ / a = 1
S
Converting a Moore to a Mealy FSMs Example
