Assignment 3 Problem with Answers - Computer Organization | EE 3755, Assignments of Electrical and Electronics Engineering

Material Type: Assignment; Professor: Skavantzos; Class: COMPUTER ORGANIZATIO; Subject: Electrical Engineering; University: Louisiana State University; Term: Spring 2008;

Typology: Assignments

Pre 2010

Uploaded on 09/17/2009

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EE3755 Homework 3 Due : April 20, 2008
Estimated time to finish:
Prob.1: 30Mins.
Total : 30Mins.
Use bgx_shell –gui
How to submit: Hard copy during the class.
Since the goal is to familiarize with the synthesizer,
this homework will not take much time to finish
Problem 1. Use the Synthesis program.
Print out or Draw the figure for the
module(100pts)
module neq_slice_es(eo,a,b,ei);
input a, b, ei;
output eo;
wire aneb, aeqb;
xor x1(aneb,a,b);
and a1(eo,aneb,ei);
endmodule
module nequal(eq,a,b);
input [3:0] a, b;
output eq;
wire e1, e2, e3;
neq_slice_es es3(e3,a[3],b[3],1'b1);
neq_slice_es es2(e2,a[2],b[2],e3);
neq_slice_es es1(e1,a[1],b[1],e2);
pf2

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EE3755 Homework 3 Due : April 20, 2008

Estimated time to finish: Prob.1: 3 0Mins. Total : 3 0Mins. Use bgx_shell –gui How to submit: Hard copy during the class.

Since the goal is to familiarize with the synthesizer,

this homework will not take much time to finish

Problem 1. Use the Synthesis program.

Print out or Draw the figure for the

module(100pts)

module neq_slice_es(eo,a,b,ei); input a, b, ei; output eo; wire aneb, aeqb; xor x1(aneb,a,b); and a1(eo,aneb,ei); endmodule module nequal(eq,a,b); input [3:0] a, b; output eq; wire e1, e2, e3; neq_slice_es es3(e3,a[3],b[3],1'b1); neq_slice_es es2(e2,a[2],b[2],e3); neq_slice_es es1(e1,a[1],b[1],e2);

neq_slice_es es0(eq,a[0],b[0],e1); endmodule