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Material Type: Assignment; Professor: Skavantzos; Class: COMPUTER ORGANIZATIO; Subject: Electrical Engineering; University: Louisiana State University; Term: Spring 2006;
Typology: Assignments
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Estimated time to finish: Prob.1: 20Mins. Prob.2 : 20Mins. Total : 4 0Mins. Use bgx_shell –gui How to submit: Hard copy during the class. Problem1. Use the Synthesis program. 1.1) Draw the figure for the module. 1.2) Look at the figure and briefly explain the functionality of the circuit. module neq_slice_es(eo,a,b,ei); input a, b, ei; output eo; wire aneb, aeqb; xor x1(aneb,a,b); and a1(eo,aneb,ei); endmodule module nequal(eq,a,b); input [3:0] a, b; output eq; wire e1, e2, e3; neq_slice_es es3(e3,a[3],b[3],1'b1); neq_slice_es es2(e2,a[2],b[2],e3); neq_slice_es es1(e1,a[1],b[1],e2); neq_slice_es es0(eq,a[0],b[0],e1); endmodule
Problem2. Use the Synthesis program, 2-1) .Draw the figure for the module compare. ( the figure maybe different(from the one at the class) when you are using bgx_shell -gui?) 2-2). Look at the figure and briefly explain the functionality of the circuit. module compare(gt, lt, a, b); input [2:0] a, b; output gt, lt; wire [2:0] a, b; reg gt, lt; integer i; always @( a or b ) begin gt = 0; lt = 0; for(i=2; i>=0; i=i-1) if( !gt && !lt ) begin if( a[i] < b[i] ) lt = 1; if( a[i] > b[i] ) gt = 1; end end endmodule // compare