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Electrical assignment for university first semester
Typology: Assignments
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(i)
f(A, B, C, D) = 𝑚
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8
10
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15
f(A, B, C, D) = 𝐴. 𝐵. 𝐶. 𝐷 + 𝐴. 𝐵. 𝐶. 𝐷 + 𝐴. 𝐵. 𝐶. 𝐷 + 𝐴. 𝐵. 𝐶. 𝐷 + 𝐴. 𝐵. 𝐶. 𝐷 +
(ii)
f
(iii) 16 - 1 multiplexer where F is the output
(iv) function f using one 4-16 decoder
(v) Using the logical expression of the function
f
f
f
f(A, B, C, D) = (𝐴 + 𝐴). 𝐵. 𝐷 + (𝐵 + 𝐴. 𝐵)𝐶. 𝐷
f
f(A, B, C, D) = 𝐵(𝐷 + 𝐶. 𝐷) + 𝐴. 𝐶. 𝐷
f(A, B, C, D) = 𝐵(𝐷 + 𝐶) + 𝐴. 𝐶. 𝐷
(vi) Using Karnaugh map for standard minterms
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f(A, B, C, D) = 𝐺
1
2
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f(A, B, C, D) = 𝐴. 𝐶. 𝐷 + 𝐵. 𝐶 + 𝐵. 𝐷
(i) This FSM is based on Mealy Machine Model, because the output depends on the present
state as well as the present input.
(ii)
Present State Input = 0 Input = 1
Next State Output Next State Output
Let S0, S1, S2 take the gray code 00, 01,10 respectively
PS - Present State
NS - Next State
I/P - Input
O/P - Output
2
1
2
1
K-Map for Y 2
2
2
1
K-Map for Y 1
1
1
1
2
K-Map for Output
1
Logisim design circuit
X 2
X 1
X 2
X 1
X 2 X 1
(i) VHDL code for GenCount unit
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity GenCount is
port (
clk : in std_logic;
reset : in std_logic;
load : in std_logic_vector((n-1) downto 0);--n bit vector
sel : std_logic_vector(1 downto 0);-- 2 bit vector
p : out std_logic;
counter : out std_logic_vector((n-1) downto 0)--n bit vector
end GenCount;
architecture Behavioral of GenCount is
signal temp : std_logic_vector((n-1) downto 0);--n-1 change
begin
Process (reset,sel,clk,load) --process for the sel signal
begin
if (reset = '1') then--asynchronous reset
temp<= x"0";--hex value
else
if(sel = "00") then
temp<= load;
elsif(sel = "11") then
temp<=temp;
else
if (falling_edge(clk)) then--triggered at falling edge of clk
if (sel = "01") then
temp <= temp + x"1"; --hex value
elsif(sel = "10") then
temp <= temp - x"1"; ----hex value
end if;
end if;
end if;
end if;
end process;
counter <= temp;
Process (temp)--Process for the output of p
begin
if (temp = 4) then
p <= '1';
else
p <= '0';
end if;
end process;
end Behavioral;
(ii) VHDL entity to model the system CompCount.
process(egg_strobe,reset,egg_size)
begin
if (reset = '1') then
A_Count<= (others=>'0');
B_Count<= (others=>'0');
C_Count<= (others=>'0');
D_Count<= (others=>'0');
else
if (rising_edge(egg_strobe) and reset ='0') then
if (egg_size = "000" or egg_size = "001" or egg_size = "010") then
A_Count<=A_Count + '1';
if (A_Count= "1100") then
A_count<=("0001");
end if;
elsif (egg_size = "011" or egg_size = "100") then
B_Count<=B_Count + '1';
if (B_Count= "1100") then
B_count<=("0001");
end if;
elsif (egg_size = "101" or egg_size = "110") then
C_Count<=C_Count + '1';
if (C_Count= "110") then
C_count<=("001");
end if;
elsif (egg_size = "111") then
D_Count<=D_Count + '1';
if (D_Count= "110") then
D_count<=("001");
end if;
end if;
end if;
end if;
end process;
--continued to next page
process(clk,reset,A_cnt,A_pulse_sent,A_Count)--process for Pack A full pulse
begin
if(reset='1' or A_Count/= "1100") then
A_cnt<=0;
A_pulse<='0';
A_pulse_sent <= false;
elsif(A_cnt=6 and A_Count = "1100") then
A_pulse_sent <= true;
elsif(rising_edge(clk) and A_pulse_sent=false and A_Count = "1100") then
A_cnt <=A_cnt+1;
if (A_cnt = 0) then
A_pulse <= '1';
elsif (A_cnt= 5) then
A_pulse <= '0';
end if;
end if;
end process;
process(clk,reset,B_cnt,B_pulse_sent,B_Count)--process for Pack B full pulse
begin
if(reset='1' or B_Count/= "1100") then
B_cnt<=0;
B_pulse<='0';
B_pulse_sent <= false;
elsif(B_cnt=6 and B_Count = "1100") then
B_pulse_sent <= true;
elsif(rising_edge(clk) and B_pulse_sent=false and B_Count = "1100") then
B_cnt <=B_cnt+1;
if (B_cnt = 0) then
B_pulse <= '1';
elsif (B_cnt= 5) then
B_pulse <= '0';
end if;
end if;
end process;
--continued to next page
(ii) VHDL code for test bench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.math_real.all;
ENTITY control_unit_tb IS
END control_unit_tb;
ARCHITECTURE behavior OF control_unit_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT control_unit
PORT(
egg_strobe : IN std_logic;
reset : IN std_logic;
egg_size : IN std_logic_vector(2 downto 0);
clk : IN std_logic;
Pack_A_Count : OUT std_logic_vector(3 downto 0);
Pack_B_Count : OUT std_logic_vector(3 downto 0);
Pack_C_Count : OUT std_logic_vector(2 downto 0);
Pack_D_Count : OUT std_logic_vector(2 downto 0);
Pack_A_FULL_pulse : OUT std_logic;
Pack_B_FULL_pulse : OUT std_logic;
Pack_C_FULL_pulse : OUT std_logic;
Pack_D_FULL_pulse : OUT std_logic
);
END COMPONENT;
--Inputs
signal egg_strobe : std_logic := '0';
signal reset : std_logic := '0';
signal egg_size : std_logic_vector(2 downto 0) := (others => '0');
signal clk : std_logic := '0';
--Outputs
signal Pack_A_Count : std_logic_vector(3 downto 0);
signal Pack_B_Count : std_logic_vector(3 downto 0);
signal Pack_C_Count : std_logic_vector(2 downto 0);
signal Pack_D_Count : std_logic_vector(2 downto 0);
signal Pack_A_FULL_pulse : std_logic;
signal Pack_B_FULL_pulse : std_logic;
signal Pack_C_FULL_pulse : std_logic;
signal Pack_D_FULL_pulse : std_logic;
--testbench continued
-- Clock period definitions
constant clk_period : time := 1 ns;
constant clk_period_1 : time := 10 ns;
signal feedback : std_logic:= '0';--feedback for LFSR
BEGIN
-- Instantiate the control_unit
uut: control_unit PORT MAP (
egg_strobe => egg_strobe,
reset => reset,
egg_size => egg_size,
clk => clk,
Pack_A_Count => Pack_A_Count,
Pack_B_Count => Pack_B_Count,
Pack_C_Count => Pack_C_Count,
Pack_D_Count => Pack_D_Count,
Pack_A_FULL_pulse => Pack_A_FULL_pulse,
Pack_B_FULL_pulse => Pack_B_FULL_pulse,
Pack_C_FULL_pulse => Pack_C_FULL_pulse,
Pack_D_FULL_pulse => Pack_D_FULL_pulse
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- egg_strobe process definitions
clk_process_1 :process
begin
egg_strobe <= '0';
wait for clk_period_1/4;
egg_strobe <= '1';
wait for 3*clk_period_1/4;
end process;
--testbench continued
(iii) Results of testbench
The VHDL source files for the hamming code
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity hamming_encoder is
port
clk,reset : in std_logic;
data_in : in std_logic_vector(0 to 7); --d0 d1 d2 d3 d4 d5 d6 d
ham_out_bit : out std_logic_vector(0 to 7) -- hamming code output
end hamming_encoder;
architecture behavioral of hamming_encoder is
signal p0, p1, p2, p3 : std_logic; --parity bits
signal full_sent : boolean := true;
signal ham_out_temp : std_logic_vector(0 to 7); --p0 p1 d0 p2 d1 d2 d3 p
begin
process(clk,reset)
begin
if(reset='1') then
--reset
ham_out_temp <=(others=>'0');
elsif(rising_edge(clk) and reset= '0') then
if (full_sent = true ) then --hamming coding first 4 bit nibble d0 d1 d2 d
--generate parity bits
p0 <= data_in(0) xor data_in(1) xor data_in(3);
p1 <= data_in(0) xor data_in(2) xor data_in(3);
p2 <= data_in(1) xor data_in(2) xor data_in(3);
p3 <= p0 xor p1 xor data_in(0) xor p2 xor data_in(1) xor data_in(2) xor data_in(3);
--constructing the hamming code for the first nibble p0 p1 d0 p2 d1 d2 d3 p
ham_out_temp(0 to 7) <= (p0,p1,data_in(0),p2,data_in(1),data_in(2),data_in(3),p3);
--the hamming code of first nibble was sent but second nibble still to be sent
full_sent <= false;
elsif (full_sent = false) then --hamming coding second 4 bit nibble d4 d5 d6 d
--generate parity bits
p0 <= data_in(5) xor data_in(5) xor data_in(7);
p1 <= data_in(4) xor data_in(6) xor data_in(7);
p2 <= data_in(5) xor data_in(6) xor data_in(7);
p3 <= p0 xor p1 xor data_in(4) xor p2 xor data_in(5) xor data_in(6) xor data_in(7);
--constructing the hamming code for the second nibble p0 p1 d4 p2 d5 d6 d7 p
ham_out_temp(0 to 7) <= (p0,p1,data_in(4),p2,data_in(5),data_in(6),data_in(7),p3);
--the hamming code for both nibbles sent confirmation
full_sent <= true;
end if;
end if;
end process;
--code continued to next page
Simulation results of the hamming encoder
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset<='1';
wait for 100 ns;
reset<='0';
wait for clk_period*10;
-- insert stimulus here
data_in<="10111000";
wait for clk_period*2;
data_in<="01011011";
wait for clk_period*2;
data_in<="00000001";
wait;
end process;
--end of test bench
