Docsity
Docsity
Prepare for your exams
Prepare for your exams

Study with the several resources on Docsity

Earn points to download
Earn points to download

Earn points by helping other students or get them with a premium plan

Guidelines and tips
Guidelines and tips
Sell on Docsity
Sell on Docsity
Docsity AI
Docsity AI
Log inSign up

Prepare for your exams

Study with the several resources on Docsity

Find documents

Prepare for your exams with the study notes shared by other students like you on Docsity

Search for your university

Find the specific documents for your university's exams

Docsity AINEW

Summarize your documents, ask them questions, convert them into quizzes and concept maps

Explore questions

Clear up your doubts by reading the answers to questions asked by your fellow students

Earn points to download

Earn points by helping other students or get them with a premium plan

Share documents
download point icon20 Points

For each uploaded document

Answer questions
download point icon5 Points

For each given answer (max 1 per day)

All the ways to get free points
Get points immediately

Choose a premium plan with all the points you need

Study Opportunities

Choose your next study program

Get in touch with the best universities in the world. Search through thousands of universities and official partners

Community

Ask the community

Ask the community for help and clear up your study doubts

Free resources

Our save-the-student-ebooks!

Download our free guides on studying techniques, anxiety management strategies, and thesis advice from Docsity tutors

Stimulus - HDL Design - Lecture Slides, Slides of Verilog and VHDL

During the course work of the HDL design, the key points in the lecture slides are:Stimulus, Response, Response of a Design, Verifying Output, Signal Sampling, Automating Output Verification, Golden Vectors, Output Timing, Deadlock and Deadlock, Predicting the Output

Typology: Slides

2012/2013

Uploaded on 05/07/2013

anjaliy
anjaliy 🇮🇳

4.5

(17)

139 documents

1 / 20

Toggle sidebar

This page cannot be seen from the preview

Don't miss anything!

bg1
Lect 11 - Stimulus & Response
•Checking the response of a design
•Verifying output – using listings and waveforms
•Signal Sampling
•Automating output verification
•Golden vectors and output timing
•Deadlock and deadlock recovery
•Predicting the output
Docsity.com
pf3
pf4
pf5
pf8
pf9
pfa
pfd
pfe
pff
pf12
pf13
pf14

Partial preview of the text

Download Stimulus - HDL Design - Lecture Slides and more Slides Verilog and VHDL in PDF only on Docsity!

Lect 11 - Stimulus & Response

  • Checking the response of a design
  • Verifying output – using listings and waveforms
  • Signal Sampling
  • Automating output verification
  • Golden vectors and output timing
  • Deadlock and deadlock recovery
  • Predicting the output

Verifying Output

  • Generating stimulus is only half of the job. Actually, it is about only 30% of the job. You control the value and timing of the stimulus.
  • Knowing the value and timing of the output given an input, or a sequence of inputs, is key to performing verification
  • Verifying that the output is as expected
    • is more time consuming
    • is more error prone
  • Specific points in time that are significant differ from design to design

Signal Waveforms

  • Also allow visual inspection of results
  • Without showing expected value of signal, can be very hard to find errors

Listings and Waveforms

  • Should log significant signals
  • Should log signals at appropriate times
  • The signals which are significant, and the times at which they are important, changes as the simulation progresses
  • Should always list/display the expected value of the significant signals

When to Sample?

  • Simplest technique: sample relevant signals at regular intervals
  • Interval can be
    • Periodic, i.e., simply time
    • Based on a reference signal such as a clock
    • Based on whenever one signal in a set of signals changes

Inspection of Waveform

  • Visual inspection, without the expected result, is prone to error. Even with the expected result, visual inspection can allow for errors being missed
  • How long would it take to notice error? And this is for a D F/F with a 2-to-1 mux on the data inputs

Golden Vectors

  • A set of reference output results determined to be correct.
  • May be used in HDL simulations
  • May be used in/with other tools to check for the validity of the result
  • Can become invalid and no longer help if the design specification changes

Output Timing

  • To properly and completely verify the functionality of a design, - must also verify the output stays stable as specified, - the value of the output is as specified, - the timing of the output is as specified
  • For busses may need to insure bus is at high- impedance (Z) prior to a signal value, the signal value is then applied and held until the bus again returns to high-impedance.

Deadlock

  • If feedback from the design under test is used to apply the test(s) then deadlock becomes possible.
  • If the design under test does not provide the feedback as expected, stimulus generation may be halted.
  • If deadlocked, you are waiting on a condition that will never occur.
  • If deadlocked, the simulation may still be running and the logging of some signals may still be taking place, but anything useful is not!!

Deadlock Recovery

  • If deadlock is possible must make sure simulation halts or at least identifies what has occurred.

Predicting (Knowing) the Output

  • Unstated assumption of self-checking testbenches is that you know the output to be produced, given the inputs.
  • Sometimes output prediction is
    • Easy – RAM, ROM, adders, …
    • Hard – Video compressor, speech synthesizer, …
  • Knowing the response is key to verification.

Classes of Designs –

Data Formatters

  • Predicting the output is dependent on the device/system/ sub-system/… being verified.
  • Data Formatters – class of designs where the input information is not transformed, simply reformatted

Classes of Designs –

Packet Processors

  • Family of designs that use some of the input information for processing, sometimes transforming it. The remainder is untouched and sent to the output.
  • Examples – Ethernet hubs, ATM switches, etc.

Output monitors assure the packet is correctly processed

Classes of Designs –

Complex Transformations

  • Design processes and transforms the input data completely and thoroughly to produce outputs that may differ in both data, timing, and the number of outputs per input.
  • Must either hand compute output(s) or use an alternative model (may even be written in another language, such as C or C++)