Binary Decision Diagram - Design Verification and Test - Lecture Notes, Study notes of Design and Analysis of Algorithms

Main points of Design Verification and Test are: Binary Decision Diagram, Gate Level, Circuit Implementation, Terms of Transistors, Perform, Specifications, Implement, Change Specifications, Versions, Equivalent

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Module-VI
Lecture-I
Binary Decision Diagram: Introduction and construction
1. Introduction
As discussed in the “Design” part of the course, digital VLSI design flow can be sub-divided
into two parts, namely frontend and backend. Frontend part starts with design specifications
and generates gate level circuit implementation. Backend part starts with the gate level circuit
and finally produces layout of the circuit in terms of transistors, power lines, I/O pads etc.
which is used for fabrication; in this course we have not covered the backend part of the
design flow. In case of both frontend and backend, we perform many transformations,
however, it is mandatory that equivalence in terms of specifications are to be maintained
across transformations. In other words, the final design should implement the intent provided
in the specifications. So, to ensure that transformations do not change specifications,
equivalence is to be established between two versions of a circuit, before and after
transformation, e.g., gate level version is to be equivalent with the register transfer level
version.
A circuit having n inputs as 123
, , ... n
iii i and m outputs as 123
, , ... m
ooo o can be represented in
many ways which can be directly used for equivalence checking (with other versions). The
simplest way is to use truth tables [1]. The truth table comprises 2n rows starting from
123
0, 0, 0... 0
n
iii i to 123
1, 1, 1... 1
n
iii i (each row corresponds to an input
combination). Also output values of 123
, , ... m
ooo o for the corresponding input combinations
are stored. Once we have truth tables of both the circuit versions, we just need to see that
output values of both the truth tables are same for each corresponding row (i.e.,
combinations).
Another technique to represent digital circuits is to use Binary Decision Trees (BDT) [2].
Corresponding to each output 123
, , ... m
ooo o there is binary tree. There are 2n leaf nodes of
each tree, and each leaf node (for the tree corresponding to 1
o, say) represents a value of 1
o
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Module-VI

Lecture-I

Binary Decision Diagram: Introduction and construction

1. Introduction As discussed in the “Design” part of the course, digital VLSI design flow can be sub-divided into two parts, namely frontend and backend. Frontend part starts with design specifications and generates gate level circuit implementation. Backend part starts with the gate level circuit and finally produces layout of the circuit in terms of transistors, power lines, I/O pads etc. which is used for fabrication; in this course we have not covered the backend part of the design flow. In case of both frontend and backend, we perform many transformations, however, it is mandatory that equivalence in terms of specifications are to be maintained across transformations. In other words, the final design should implement the intent provided in the specifications. So, to ensure that transformations do not change specifications, equivalence is to be established between two versions of a circuit, before and after transformation, e.g., gate level version is to be equivalent with the register transfer level version.

A circuit having n inputs as i 1 (^) , i 2 (^) , i 3 ... i (^) n and m outputs as o 1 (^) , o 2 (^) , o 3 ... om can be represented in many ways which can be directly used for equivalence checking (with other versions). The simplest way is to use truth tables [1]. The truth table comprises 2 n^ rows starting from i 1 (^)  0, i 2 (^)  0, i 3  0... i (^) n  0 to i 1 (^)  1, i 2 (^)  1, i 3  1... i (^) n  1 (each row corresponds to an input combination). Also output values of o 1 (^) , o 2 (^) , o 3 ... o (^) m for the corresponding input combinations are stored. Once we have truth tables of both the circuit versions, we just need to see that output values of both the truth tables are same for each corresponding row (i.e., combinations).

Another technique to represent digital circuits is to use Binary Decision Trees (BDT) [2]. Corresponding to each output o 1 (^) , o 2 (^) , o 3 ... o (^) m there is binary tree. There are 2 n^ leaf nodes of each tree, and each leaf node (for the tree corresponding to o 1 , say) represents a value of o 1

for an input combination. Input combination for a leaf node is determined by the path from root to the leaf node under question, which comprises n non-leaf nodes, one for each input variable i 1 (^) , i 2 (^) , i 3 ... in. If the left (right) path is taken from the non-leaf node corresponding to an

input i 1 say, then the value for i 1 is 0 (1). Similarly, conditions for all inputs i 1 (^) , i 2 (^) , i 3 ... in can

be determined for a leaf node. Now, if two circuit versions are to be equivalent, then all the binary decision trees for o 1 (^) , o 2 (^) , o 3 ... o (^) m are to be same (exact image) for both the versions.

It may be noted that once a truth table or binary decision tree is created, equivalence checking is very simple, involving a matter of checking exact match of the corresponding elements. However, the major problem is in creating and maintaining the binary decision tree of the truth table. A circuit having n inputs and m outputs has O (2 nm )entries in the truth

table; 2 n^ rows and m outputs for each row. Similarity, for such a circuit the number of nodes

in the BDT is O ((2 n^ ^1  2 ) nm )[2]. Any practical VLSI circuit may easily contain 100s of

inputs and outputs, thereby making construction of binary decision tree or truth table impossible within practical time lines. It may be noted that although digital circuits can be represented efficiently using Boolean functions [1], but they cannot be directly used for equivalence checking (which was the case in binary trees and truth tables). For example, Boolean functions “x+0” and “x” (x is a Boolean variable) are equivalent even if they look structurally different. To cater to the issue of high complexity in generating binary decision tree or truth table, a new data structure called Ordered Binary Decision Diagram (OBDD) was proposed by R.E. Bryant [3]. Broadly speaking an OBDD comprises much lower number of nodes compared to 2 n^ , (for a circuit having n inputs) and at the same time two equivalent circuits will generate the same OBDD (which can be directly used for comparison). In this module, we will study in details about OBDDs, comprising basic introduction, construction algorithm, operations on OBDDs and representation of sequential circuits. In the first lecture we will start with an introduction to OBDDs.

a b b c c^ c c

d d d d d^ d d^ d

0 0 0 1 0 0 0 1 0 0 0 1 1 1 1 1

Figure 2. Binary decision tree for f ( , , , a b c d ) abcd From the function it may be noted that if abcd  0 then the function evaluates to 0; this is represented by the path “start from a , left edge to b , left edge to c , left edge to d and left edge to leaf node 0. Also, if a  1, b  1, cd  0 then the function evaluates to 1; this is represented by the path “start from a , right edge to b , right edge to c , left edge to d and left edge to leaf node 1.

As already mentioned, truth table as well as BDT representation of Boolean expressions are not of much benefit because of exponential growth of the table and the tree.

3. Binary Decision Diagrams From the example illustrated in the last section, it may be noted that BDT cannot be generated within practical time lines for a reasonably complex circuit. The main reason is the exponential number of nodes in a BDT with respect to number of inputs. However, it may be noted that there are many redundant nodes in the BDT; simply, in the leaf level we can have one node with “0” and the other with “1” and redirect paths from the nodes of leaf level - accordingly. Similarly, this reduction is carried out at all layers till the root. Broadly speaking, a Binary Decision Diagram (BDD) is a directed acyclic graph representation of the Boolean expression which cannot further be reduced my eliminating redundant nodes. In other words, just like BDT, BDD is an acyclic graph representation of a Boolean expression but unlike BDT, it does not comprise any redundant node either in the leaf or the non-leaf level. So BDD is called Reduced BDD (RBDD). The reduction from BDT to RBDD is done using three rules.  R1: Removing of duplicate terminals (leaf nodes): If a BDD contains more than one terminal 0-node, then we redirect all edges which point to such 0-node to just one of them and other 0-node can be removed. Similarly we do with 1-node also.  R2: Removal of duplicate non terminals (internal nodes): If two distinct nodes n and m in the RBDD are the roots of structurally identical sub-BDDs, then we eliminate one of them, say m , and redirect all its incoming edges to the other one (node n )  R3: Removal of Redundant test: If both outgoing edges of a node n point to the same node m , then we eliminate the node n , and point all its incoming edges to m. After application of Rule R1, Rule R2 and Rule R3 repeatedly we get the reduced BDD (from BDT). A BDD is said to be reduced if none of the above rules can be applied further. (i.e., no more reduction is possible).

Now we illustrate application of the above three rules for the BDT of Figure 2.

Figure 3 illustrates the intermediate BDD when R1 is applied to the BDT of Figure 2. It may be noted that there is only one leaf node with “0” and another one with “1”. From Figure 2 it may be observed that the path from root to leaf node corresponding abcd  0 reaches a leaf node with “0”. Also the path from corresponding to abc  0; d  1 reaches a leaf

a b b

c c

d d^ d

0 1 Figure 4. Removal of Duplicate non terminals a b b c c^ c^ c d d d d d^ d^ d^ d

0 1

a b b c c^ c^ c d d d d d^ d^ d^ d

0 1

Figure 5. A pair of duplicate sub-BDDs (enclosed by polygons) in the intermediate BDD of Figure 3

a

b (^) b c c c

d d^ d^ d^ d^ d

0 1

Figure 6. Intermediate BDD after applying R2 to the duplicate sub-BDDs shown in Figure 5

From Figure 4 it may be noted that there nodes n say, where both the outgoing edges point to the same node m say ; R3 eliminates such a node n and points all its incoming edges to m. Nodes of such type in BDD of Figure 4 are marked and shown in Figure 7. Figure 8 illustrates the intermediate BDD when R3 is applied to node “b” (marked by an arrow) whose both the outgoing edges point to the same node “c”. When R3 is applied to all such nodes, the BDD obtained is shown in Figure 9. a b b

c c

d d^ d

0 1 Figure 7. Nodes (arrow marked) where both the outgoing edges point to the same node

4. RBDD using Shannon expansion In the last section we demonstrated that a RBDD comprises much less number of nodes compared to its equivalent BDT. However, the construction started from a BDT and was finally transformed to a RBDD. As already discussed, time taken to generate a BDT is prohibitive for even a function with reasonable complexity. To obtain RBDD, it is not necessary to start with BDT at the first place. The discussion in the last section was only to illustrate that RBDD is a BDT without any redundancy and there are lots of redundant nodes in a BDT. Now we discuss how RBDD can be generated directly without use of a BDT. RBDD is based on Shannon Expansion, according to which Boolean function can be represented by the sum of two sub-functions of the original. In particular, a function f(x) can be written as: f ( ) xx f. [1/ x ]  x '. f [0 / x ], where x’ means complement of x and f[1/x] and f[0/x] mean function obtained on replacing the variable x with 1 and 0 respectively. For example, if f ( ) aacbcab , then f [1/ a ]  1. cbc  1. bbcbc and f [0 / a ]  0  bc  0 , so that finally f(a) can be written as: f ( ) aa b .(  cbc )  a '( bc ). If we expand a b .(  cbc )  a '( bc ), we get abacabca bc '  abacbc a .(  a '), which is abbcac ( the form of f(a), we started with ).

The basic or primitive BDDs to represent Boolean function are given below. B 0 : represents the Boolean constant 0. B 1 : represents the Boolean constant 1. B x : represents the Boolean variable x. These primitive BDDs are shown in Figure 11. x

B0 B

Bx Figure 11. Primitive BDDs

Diagrammatically, a BDD of a function of variable a is rooted at a node representing variable a , and its children represent the two sub-functions whose sum results in the original expression. The child of the root with dotted line from parent represents f[0/a] and the one with solid line from parent represents f[1/a]. BDD of a function of variable a is shown in Figure 12.

a a

f[0/a] f[1/a]

Figure 12. BDD of a function of variable a

For instance, for the above considered example (i.e., f ( ) aacbcab ) the initial diagram

would be of the form shown in Figure 13.

a

bc b+c+bc

Figure 13. Initial diagram of the function f ( ) aacbcab

Further expansion of the sub-functions would lead to the following expressions, which are to be found out till we find the leaf node of the diagram (that is binary 0 or 1): Let f [1/ a ]  bcbcg b ( )and f [0 / a ]  bch b ( ),

g [1/ b ]  1  c  1. c  1 and g [0 / b ]  ci c ( ) h [1/ b ]  ci c ( )and h [0 / b ]  0 i [1/ c ]  1 and i [0 / c ]  0

Consider another example for the Boolean function f ( , a b , c )  acbc.

[0 / ] ( ) [1/ ] ( ) [0 / ] 0 [1/ ] ( ) [0 / ] ( ) [1/ ] ( ) [0 / ] 0 [1/ ] 1

f a bc g b f a c bc h b g b g b c k c h b c k c h b c k c k c k c

The diagram for the function built using Shannon’s expansion is shown in Figure 16; the leaf level redundancies are eliminated using R1. In this case, it may be noted that there is another redundant node (encircled in Figure 16) and R2 can be applied. The final reduced BDD is shown in Figure 17.

Figure 16. Diagram of the function f ( , a b , c )  acbc after applying R

Figure 17. Final diagram (RBDD) of the function f ( , a b , c )  acbc

Question and Answers

Question:

Formal definition of BDD does not restrict recurrence of a variable in the diagram any number of times. However, this can lead to redundant decisions taken at later stages. Illustrate this concept with an example.

Answer:

Example of a BDD with redundant decision is shown in Figure 18, where variable Y is tested twice along the same path X-Y-Z-Y. Consider the following two paths in the BDD of Figure 18 Path-1 : x-y-z-y- Path-2: x-y-z-y- If we consider Path-2, then variable y is tested and taken the value to be 0 in first instance. Now along the path y is tested again and this time the value of y is considered to be 1. So, in this computation path, the truth value for y is considered to be 0 first and then as 1, which is not possible. This path is treated as inconsistent path. In such type of situation, we need to consider only consistent path. A consistent path is one which, for every variable, has only dashed line or only solid line leaving nodes labeled by that variable. In other words, it is not possible to assign a variable the values 0 and 1 simultaneously. But if we restrict the order of occurrence of variables from root to leaves, then along each path from top to bottom, each variable will occur only once and there would not be any redundant decision. Such diagram is called Ordered Binary Decision Diagram or OBDD.

x

y

y

z

z

y

0 1

Figure 18. Example of a BDD with redundant decision

Module-VI

Lecture-II

Ordered Binary Decision Diagram

1. Introduction In the previous lecture we have discussed how an RBDD represents a Boolean function, similar to truth table or Binary decision tree, however, the number of nodes do not grow exponentially with increase in number of inputs of the function. So RBDD is suitable for representing Boolean functions. It was also stated in the lecture that ordering of variables in the context of RBDD is important because  Number of nodes for a given Boolean function depends on the ordering  There may be inconsistent paths in the BDD if there is no ordering. In this lecture we will discuss Ordered BDD (which also called Ordered Reduced BDD).                           

2. Ordered OBDD An ordered BDD (OBDD) is a BDD which has an ordering for the variables of the Boolean function it is representing. Let [ x 1 ,... , xn ] be an ordered list of variables without duplications and let B be a BDD all of whose variables (of the corresponding Boolean function) occur somewhere in the list. We say that B has the ordering [ x 1 ,... , xn ] if all variable labels of B occur in that list and, for every occurrence of x (^) i followed by x (^) j along any path in B , we have i < j. In other words, BDD B has the ordering [ x 1 ,... , xn ], if the root node corresponds to variable x 1 , nodes of level 2 correspond to x 2 and so on, till the nodes of level leaf-1 correspond to xn. The BDD B1 of Figure 1 has the variable ordering [X 1 , X 2 , X 3 , X 4 , X 5 ] and the BDD B2 of Figure 2 has the variable ordering [X 5 , X 4 , X 3 , X 2 , X 1 ].

X 1

X 2

X 3

X 3

X 4 X 5

0 1 Figure 1. OBDD B1 with the variable ordering [X 1 , X 2 , X 3 , X 4 , X 5 ]