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Module-XI
Lecture-I and II
Built in Self Test
1. Introduction
Till now we have been looking into VLSI testing, only from the context where the circuit needs to be put to a “test mode” for validating that it is free of faults. Following that, the circuits tested OK are shipped to the customers with the assumption that they would not fail within their expected life time; this is called off-line testing. In other words, in off- line testing, a circuit is tested once and for all, with the hope that once the circuit is verified to be fault free it would not fail during its expected life-time. However, this assumption does not hold for modern day ICs, based on deep sub-micron technology, because they may develop failures even during operation within expected life time. To cater to this problem sometimes redundant circuitry are kept on-chip which replace the faulty parts. To enable replacement of faulty circuitry, the ICs are tested before each time they startup. If a fault is found, a part of the circuit (having the fault) is replaced with a corresponding redundant circuit part (by re-adjusting connections). Testing a circuit every time before they startup, is called Built-In-Self-Test (BIST). In this module we will study details of BIST. Once BIST finds a fault, the readjustment in connections to replace the faulty part with a fault free one is a design problem and would be not be discussed here.
2. Basic architecture of BIST As discussed in the last section, BIST is basically same as off-line testing using ATE where the test pattern generator and the test response analyzer are on-chip circuitry (instead of equipments). As equipments are replaced by circuitry, so it is obvious that compressed implementations of test pattern generator and response analyzer are to be designed. The basic architecture of BIST is shown in Figure 1.
CUT with DFT
Input MUX
Normal Input
Hardware Test Patten Generator
Outputs Output Response Compactor Primary Outputs
Comparator Signature
Status
ROM Golden Signature
Test Controller
Start BIST
Figure 1. Basic architecture of BIST
As shown in Figure 1, BIST circuitry comprises the following modules (and the following functionalities)
- Hardware Test Pattern Generator: This module generates the test patterns required to sensitize the faults and propagate the effect to the outputs (of the CUT). As the test pattern generator is a circuit (not equipment) its area is limited. So storing and then generating test patterns obtained by ATPG algorithms on the CUT (discussed in Module XI) using the hardware test pattern generator is not feasible. In other words, the test pattern generator cannot be a memory where all test patters obtained by running ATPG algorithms (or random pattern generation algorithms) on the CUT are stored and applied during execution of the BIST. Instead, the test pattern generator is basically a type of register which generates random patterns which act as test patterns. The main emphasis of the register design is to have low area yet generate as many different patterns (from 0 to 2 n^ , if there are n flip-flops in the register) as possible.
3. Hardware pattern generator
As discussed in the last sub-section, there are two main targets for the hardware pattern generator—(i) low area and (ii) pseudo-exhaustive pattern generation (i.e., generate as many different patterns from 0 to 2 n^ as possible, if there are n flip-flops in the register). Linear feedback shift register (LFSR) pattern generator is most commonly used for test pattern generation in BIST because it satisfies the above two conditions. There are basically two types of LFSRs, (i) standard LFSR and (ii) modular LFSR. In this section we will discuss both these LFSRs in detail.
3.1 Standard LFSRs Figure 2 shows an external exclusive-OR also called standard LFSR. The circuit representation of standard LFSR is shown in Figure 3. LFSR, as the name suggests, it is basically a shift register having D flip-flops where the output of the last flip-flop provides feedback to the input of the first flip-flop. If there are n flip- flops (numbered as X (^) 0 , X (^) 1 ... X (^) n 1 ), then the LFSR is called n -stage LFSR. The feedback is basically a linear XOR function of the outputs of the flip-flops. Output of any flip-flop may or may not participate in the XOR function; if output of any flip-flop X (^) i say, provides input to the XOR function then corresponding tap point hi (Figure 2) is 1. Similarly, if output of flip-flop X (^) i does not provide input to the XOR function then corresponding tap point hi (Figure 2) is 0. In the circuit representation (Figure 3) if hi =0, then there is no XOR gate in the feedback network corresponding to the output of the flip-flop X (^) i ; otherwise, the XOR gate is included.
A properly-designed LFSR can generate as a near-exhaustive set of patters, as it can cycle through distinct 2 n^ 1 states (except 0s is all flip-flops). Such a properly designed LFSR is known as a maximal length LFSR.
DFF DFF DFF DFF
Xn-1 Xn-2 X 1 X 0
h h^1 2
h (^) n-1 h (^) n-
Figure 2. Standard LFSR
DFF DFF (^) DFF DFF
Xn-1 Xn-2 X (^1) X 0
h (^1) h (^2)
h (^) n-1 h (^) n-
D Q D Q D Q D Q
Figure 3. Circuit representation of standard LFSR
The following matrix system of equations describes the standard LFSR. 0 1
3 2 1
( 1)^0 0 0......0^1
( 1)^1
n n n
X t
X t
X t
X t
X t
0 1
3 2 1 2 -2 -1 (^1)
n n n n (^) n
X t
X t
X t
X t
h h h h X t
^
^
^
^
^
^
^
^
This LFSR in terms of the matrix can be written as X t ( 1) T X tS ( ). It may be noted the matrix TS defines the configuration of the LFSR. Leaving behind the first column and the last row TS is an identity matrix; this indicates that X (^) 0 gets input from X 1 , X (^) 1 gets input from X (^) 2 and so on. Finally, the first element in the
0 1 2
1 0 0 1 1 1 0 1 0 ::: 0 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 0 1
X X X
(^) (^) (^)
So the LFSR generates 7 patterns (excluding all 0s) after which a pattern is repeated. It may be noted that this LFSR generates all patters (except all 0s) which are generated by a 3 bit counter, however, the area of the LFSR is much lower compared to a counter. In a real life scenario, the number of inputs of a CUT is of the order of hundreds. So LFSR has minimal area compared to counters (of order of hundreds).
3.2 Modular LFSRs
Figure 5 shows an internal exclusive-OR also called modular LFSR. The circuit representation of modular LFSR is shown in Figure 6. The difference in modular LFSR compared to standard LFSR is due to the positions of the XOR gates in the feedback function; in modular LFSR XOR gates are in between adjacent flip- flops. Modular LFSR works faster than standard LFSR, because it has at most one XOR gate between adjacent flip-flops, while there can be several levels of XOR gates in the feedback of standard LFSR..
DFF DFF (^) DFF DFF X (^0) X 1 Xn-2 Xn-
h 1 h (^2)
+ + +
h (^) n-
Figure 5. Modular LFSR
DFF DFF^ DFF DFF
X 0 X 1 Xn-2 Xn-
h 1 h 2 h (^) n- D (^) Q D (^) Q D (^) Q D Q
Figure 6. Circuit representation of modular LFSR
In modular LSFR the output of any flip-flop may or may not participate in the XOR function; if output of any flip-flop X (^) i say, provides input to the XOR gate which feeds the input of flip-flop X (^) i 1 then corresponding tap point hi (Figure 5) is 1. In the circuit representation (Figure 6) of hi =1, then there is an XOR gate from output of flip-flop X (^) i to input of flip-flop X (^) i 1 ; else output of flip-flop X (^) i is directly fed to input of flip-flop X (^) i 1.
DFF DFF^ DFF DFF
X 0 X 1 X 2 X 3
h (^3)
D (^) Q D (^) Q D (^) Q D Q
Figure 7. Example of a modular LFSR
The matrix of the LFSR is as follows 0 0 1 1 2 2 3 3
( 1) 0 0 0 1 ( ) ( 1) 1 0 0 0 ( ) ( 1) 0 1 0 0 ( ) ( 1) 0 0 1 1 ( )
X t X t X t X t X t X t X t X t
(^) (^) (^) (^) (^) (^) (^) ^
The characteristic polynomial of the LFSR is f ( ) x 1 x^3^ x^4. If the initial values of the flip-flops are X (^) 0 1, X (^) 1 0, X (^) 2 0, X 3 0 then the sequence of patters is as follows: 0 1 2 3
1 0 0 0 1 1 1 1 0 1 0 1 1 0 0 1 0 0 1 0 0 0 1 1 1 1 0 1 0 1 1 0 0 1 ::: 0 0 1 0 0 0 1 1 1 1 0
X X X X
1 0 1 1 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 1 0 0
So the LFSR generates 15 patterns (excluding all 0s) after which a pattern is repeated. It may be noted that this LFSR generates all patters (except all 0s) which is generated by a 4 bit counter.
Now, the question arises, whether any LFSR would generate all 2 n^ 1 patters? The answer is no. Only for a few characteristic polynomials the LFSR is maximal length; such polynomials are called primitive polynomials (List of such polynomials can be found in Bardell et al. [2]).
4. Hardware response compactor
As discussed in Section 2 of this module, expected output (i.e., golden response) of the CUT cannot be sorted explicitly in a memory and compared with response obtained from the CUT. In other words, in BIST, it is necessary to compress the large number of CUT responses to a manageable size that can be stored in a memory and compared. In response compaction, sometimes it may happen that the compacted response of the CUT under normal and failure conditions are same. This is called aliasing during compaction. In this section we will discuss some simple techniques to compress CUT responses namely (i) number of 1s in the output and (ii) transition count at the output. For other complex techniques like LFSR based compaction, multiple input signature register based compaction, built-in logic observer based compaction etc. the reader is referred to [3,4, 5].
4.1 Number of 1s compaction Number of 1s compaction, is a very simple technique where we count the number of ones in the output responses from the CUT. Figure 8 shows a simple example of such a compaction. In Figure 8 (a), the CUT under normal condition is shown where the inputs are given by the LFSR of Figure 4. It may be noted that 7 patterns (non-similar) were generated by the LFSR, which when given as input to the CUT generates output as 0001000, making number of 1s as 1. Figure 8 (b) shows the same circuit with s-a-1 fault. When the same inputs are given to the CUT the output is 0001100, making number of 1s as 2. So fault can be detected by the compaction as there is difference in number of 1s at the output of the CUT for the given input patterns. In other words, for the input patterns (from the LFSR), “number of 1s” based compaction is not aliasing. It may be noted that corresponding to the input patters, value of 1 is stored (as golden signature) in the memory which is compared with compacted response of the CUT.
Number of 1s = 2
1001110 0011101
1000101 0111010
0000100
1100010 0000010
0000110
X 0 X 1 X 2
Number of 1s = 2
1001110 0011101
1000101 0111010
1000100
0000000 0000000
1000100
X 0 X 1 X 2 s-a-
1111101
(a) Normal Circuit
(b) Circuit with s-a-fault
Figure 9. Example of response compaction “number of 1s” -aliasing
4.2 Transition count response compaction In this method of response compaction the number of transitions from 0 to 1 and 1 to 0 at outputs of the CUT are counted. Figure 10 shows the same circuit of Figure 8, when compaction technique is “transition count”. In Figure 10 (a), the CUT under normal condition is shown where the inputs are given by the LFSR of Figure 4. The CUT generates output as 0001000, making transition count as 2; in the output sequence there is a transition from 0 to 1 and then from 1 to 0. Figure 8 (b) shows the same circuit with s-a-1 fault. When the same inputs are given to the CUT the output is 0001100, making transition count as 2. So fault cannot be detected by the compaction.
1001110 0011101 0111010
0001100 0001000
Transition Count = 2
1001110 0011101 0111010
0001100 0001100
s-a-1 Transition Count = 2
1111111
(a) Normal Circuit
(a) Circuit with s-a-1 fault
X 0 X 1 X 2
X 0 X 1 X 2
Figure 10. Example of response compaction “transition count” -aliasing
Figure 11 shows the same circuit of Figure 9 when the “transition cout” based compaction is used. In Figure 11 (a), the CUT under normal condition is shown where the input is given by the LFSR of Figure 4. The CUT generates output as 0000110, making transition count as 2. Figure 11 (b) shows the same circuit with
5. Conclusions In this lecture we have seen that modern day ICs may develop faults even after manufacturing test. So additional testing is required for assuring quality of service. BIST is such a test procedure which facilitates testing of circuits before every time they start their operations. In this module we have discussed most of the important components of BIST. Till now, in this course we were discussing about testing of digital circuits comprising Boolean gates and flip-flops. However, memory is also a very vital element for digital circuits. The structure of memory blocks are basically different compared to logic blocks. In the next lecture we will deal with testing of memory blocks.
References
- Mano, M. Morris,. Digital Design, 2/e. Prentice-Hall of India. 1995.
- P. H. Bardell, W. H. McAnney, and J. Savir, Built-In Test for VLSI: Pseudorandom Techniques. New York: John Wiley and Sons, Inc., 1987.
- R. A. Frohwerk, “Signature Analysis: A New Digital Field Service Method,” Hewlett- Packard Journal, vol. 28, no. 9, pp. 2–8, May 1977.
- S. Z. Hassen and E. J. McCluskey, “Increased Fault Coverage Through Multiple Signatures,” in Proc. of the International Fault-Tolerant Computing Symp., June 1984,pp. 354–359.
- M. Bushnell and V.D. Agrawal, “Essentials of Electronic Testing for Digital, Memory & Mixed-Signal Circuits”, Kluwer Academic Publishers, 2000
Module-XI
Lecture-III and IV
Memory Testing
1. Introduction: Why is memory testing different?
Till now we have been looking into VLSI testing, only from the context where the circuit is composed of logic gates and flip-flops. However, memory blocks form a very important part of digital circuits but are not composed of logic gates and flip-flops. This necessitates different fault models and test techniques for memory blocks. In memory technology, the capacity quadruples roughly every 3 years [1], which leads to decrease in memory price per bit (being stored). It is to be noted that increase in capacity does not lead to a proportional rise in area of a memory chip. In other words, high storage capacity is obtained by raise in density, which implies decrease in the size of circuit (capacitor) used to store a bit. Experiments with new materials having high dielectric constant like barium strontium titanate [2] are being done that facilitate greater capacitance to be maintained in the same physical space. Also, design and layout techniques like stacked capacitors are being tried to achieve higher density. Further, for faster access of the memory, various methods are being developed which includes fast page mode (FP), extended data output (EDO), synchronous DRAM (SDRAM), double data rate etc. So, modern memory designs aim at high capacity at lower area and fast access speed. This leads to a situation where we have very less charge stored per memory cell (because of low capacitance), and cells are extremely close to each other. Further, due to use of deep micron technology the cells are becoming more susceptible to manufacturing defects. So, unlike normal circuits where we generally do not have faults (or chips having faults are discarded), multiple faults will be present in any memory chip. In other words, the yield of memory chips would be nearly 0%, since every chip has
defects. During manufacturing test, the faults are not only to be detected but also their locations (in terms of cell number) are to be diagnosed. As almost all memories will have faults in some cells, there are redundant (extra) cells in the memory. One a fault is diagnosed, the corresponding cell is disconnected and a new fault free cell is connected in the appropriate position. This replacement is achieved by blowing fuses (using laser) to reroute defective cells to normal spare cells. The sole functionality of a cell is to sore a bit information which is implemented using a capacitor; when the capacitor is charged it represents 1 and when there is no charge it represents 0. No logic gates are involved in a memory. Use of logic gates (in flip-flops) instead of capacitors to store bit information would lead to a very large area. The above two points basically differentiate testing of logic gate circuits from memory. So, new fault models and test procedures are required for testing memories. In this lecture we will study the most widely used fault models and test techniques for such fault models in memories.
