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ECE 545—Digital System Design with VHDL
Bit-Counter ASM Example
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Bit-Counting – Required Interface
Bit-Counter
Clock
Resetn
Data N
B
log2(N)
Done
S
(0=transfer data
1=computations)
Specification: Count the number of 1’s in Data
LA
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VHDL Bit-Counter Design: Pseudocode, ASM, Diagram, and Controller - Prof. David Hwang, Study notes of Digital Systems Design
The design details of a bit-counter using vhdl, including pseudocode, high-level asm, datapath block diagram, and controller asm. The bit-counter is designed to count the number of 1's in an n-bit input data. The functionality of each port, the logic behind the design, and the step-by-step implementation.
Typology: Study notes
Pre 2010
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ECE 545—Digital System Design with VHDL
Bit-Counter ASM Example
Bit-Counting – Required Interface
Bit-Counter
Clock
Resetn
Data^ N^ log2(N) B
Done
S (0=transfer data
1=computations)
Specification: Count the number of 1’s in Data
LA
Explanation of ports
• Inputs • Clock : the circuit clock
• • ResetnData : N-bit input: asynchronous circuit reset (active-low)
• • LAS : system mode: 1= load data at next rising clock edge, 0 = do not load data
• • 0 = write data initially or read results1 = do computations
• Outputs • B : log2(N)-bit output.
• Done : Indicates the operation is done.
Step 1: Pseudocode
B while = 0 ; A ≠ 0 do
if a^ 0 = 1 then B = B + 1 ;
End if;Right-shift A ;
End while;
[load data into A]
[send done flag]
Data N Clock Resetn
B
log2(N)
s
Done
za
EALB
EB
Datapath Controller
Step 4: Top-Level Interface Diagram
LA
Step 5: Detailed Controller ASM
EA
EB z
LB
s
a (^) 0
Reset
S
(^0) s 1 S
S
Done
n