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Vhdl code examples for designing combinational logic blocks using process statements, including a majority gate, a multiplexer with don't care conditions, and a priority encoder. It also discusses common mistakes and best practices in modeling combinational logic using process statements.
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Outline
Resources
VHDL Design Styles (Architecture)
components and interconnects
VHDL Design Styles
“concurrent” statements (^) • Sequential Logic
“sequential” statements
Majority Gate
Majority Gate—Dataflow
library IEEE; use IEEE.STD_LOGIC_1164.all;
entity majority1 is port( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; f : out STD_LOGIC ); end majority1;
architecture dataflow of majority1 is begin f <= (a and b) or (a and c) or (b and c); end dataflow;
Testbench
library ieee; use ieee.std_logic_1164.all;
entity majority1_tb is end majority1_tb;
architecture TB_ARCHITECTURE of majority1_tb is
component majority port( a : in std_logic; b : in std_logic; c : in std_logic; f : out std_logic ); end component;
signal a : std_logic := '0'; signal b : std_logic := '0'; signal c : std_logic := '0'; signal f : std_logic;
Testbench cont'd
begin
UUT : majority1 port map (a => a, b => b, c => c, f => f);
process begin for i in 0 to 1 loop for j in 0 to 1 loop for k in 0 to 1 loop wait for 10 ns; c <= not c; end loop; b <= not b; end loop; a <= not a; end loop; wait; end process;
end TB_ARCHITECTURE;
Testbench—Another Method cont'd
begin UUT : majority1 port map (a => a, b => b, c => c, f => f);
a <= inputvec(2); -- assign ports b <= inputvec(1); c <= inputvec(0); process begin inputvec <= "000"; -- initialize for i in 0 to 7 loop wait for 10 ns; inputvec <= inputvec + 1; end loop; wait; end process;
end TB_ARCHITECTURE;
Combinational Logic Using Process Statements
1. Make sure all inputs (all things on right-hand side of an equation) are listed in process sensitivity list **MISTAKE # 1
Examples illustrate mistakes
mistakes
Waveform – Error # 1
Mistake # 2 – Not all outputs assigned value
library IEEE; use IEEE.STD_LOGIC_1164.all; entity majority1 is port( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; f : out STD_LOGIC ); end majority1; architecture behavioral of majority1 is begin process (a,b,c) begin if (((a = '1') and (b = '1')) or ((a = '1') and (c = '1')) or ((b = '1') and (c = '1')) ) then f <= '1'; -- no default value assigning f <= '0' end if; end process; end behavioral;
Waveform – Error # 2
Mux with Don't Cares with Process Statements
(Correct) cont'd
architecture behavioral of muxdontcare is signal selint : integer range 0 to 3; begin selint <= conv_integer(unsigned(sel)); process (a,b,c,d,selint) begin if (selint = 0) then x <= a; y <= '0'; elsif (selint = 1) then x <= b; y <= '1'; elsif (selint = 2) then x <= c; y <= '-'; -- use '-' to indicate don't care else -- selint is 3 x <= d; y <= '-'; -- use '-' to indicate don't care end if; end process; end behavioral;
Testbench
library ieee; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use ieee.std_logic_1164.all;
entity muxdontcare_tb is end muxdontcare_tb;
architecture TB_ARCHITECTURE of muxdontcare_tb is
component muxdontcare port( a : in std_logic; b : in std_logic; c : in std_logic; d : in std_logic; sel : in std_logic_vector(1 downto 0); x : out std_logic; y : out std_logic ); end component;
Testbench cont'd
signal a,b,c,d,x,y : std_logic; signal sel : std_logic_vector(1 downto 0); signal inputvec : std_logic_vector(3 downto 0); begin UUT : muxdontcare port map ( a => a, b => b, c => c, d => d, sel => sel, x => x, y => y ); a <= inputvec(3); b <= inputvec(2); c <= inputvec(1); d <= inputvec(0); process begin inputvec <= "0000"; sel <= "00"; for i in 0 to 3 loop for j in 0 to 15 loop wait for 10 ns; inputvec <= inputvec + 1; end loop; sel <= sel + 1; end loop; wait; end process; end TB_ARCHITECTURE;
Waveform
Mistake # 2 – Not all outputs assigned value cont'd
architecture behavioral of muxdontcare is signal selint : integer range 0 to 3; begin selint <= conv_integer(unsigned(sel)); process (a,b,c,d,selint) begin if (selint = 0) then x <= a; y <= '0'; elsif (selint = 1) then x <= b; y <= '1'; elsif (selint = 2) then x <= c; -- don't assign y else -- selint is 3 x <= d; -- don't assign y end if; end process; end behavioral;
Waveform – Mistake #
Testbench
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity priority_tb is end priority_tb; architecture TB_ARCHITECTURE of priority_tb is component priority port( y : in std_logic_vector(7 downto 1); pout : out std_logic_vector(2 downto 0) ); end component; signal y : std_logic_vector(7 downto 1); signal pout : std_logic_vector(2 downto 0); begin UUT : priority port map ( y => y, pout => pout );
Testbench cont'd
process begin y <= "0000000"; for i in 1 to 128 loop wait for 10 ns; y <= y + 1; end loop; wait; end process; end TB_ARCHITECTURE;
Waveform
Priority Encoder—Correct but be careful
library ieee; use ieee.std_logic_1164.all; entity priority is port ( y: in std_logic_vector(7 downto 1); pout: out std_logic_vector(2 downto 0) ); end priority; architecture behavioral of priority is begin process (y) begin pout <= "000"; if (y(1) = '1') then pout <= "001"; end if; if (y(2) = '1') then pout <= "010"; end if; if (y(3) = '1') then pout <= "011"; end if; if (y(4) = '1') then pout <= "100"; end if; if (y(5) = '1') then pout <= "101"; end if; if (y(6) = '1') then pout <= "110"; end if; if (y(7) = '1') then pout <= "111"; end if; end process; end behavioral;
