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ECE 545—Digital System Design with VHDL
Lecture 2
Combinational Logic Review
Announcements
Today’s Schedule:
- From 4:30 - 5:45 PM:
- Students with last names (surnames) that begin with A-M,
meet in Krug Hall Room 19 for lecture
- Students with last names (surnames) that begin with N-Z,
meet in ST2 Room 203 for the hands-on session
- From 5:45 - 5:55 PM: Break, switch sessions.
- From 5:55 - 7:10 PM:
- Students with last names (surnames) that begin with A-M,
meet in ST2 Room 203 for the hands-on session
- Students with last names (surnames) that begin with N-Z,
meet in Krug Hall Room 19 for lecture
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Lecture Roadmap
• Basic Logic Review
• Basic Gates (AND,OR,XOR,NAND,NOR)
• DeMorgan’s Law
• Combinational Logic Blocks
• Multiplexers
• Decoders, Demultiplexers
• Encoders, Priority Encoders
• Half Adders, Full Adders
• Multi-Bit Combinational Logic Blocks
• Multi-bit multiplexers
• Multi-bit adders
• Comparators
Basic Logic Review
some slides modified from:
S. Dandamudi, “Fundamentals of Computer Organization and Design”
7
Basic Logic Gates
Number of Functions
- Number of functions
- With N logical variables, we can define
2 2
N functions
- Some of them are useful
- Some are not useful:
- Output is always 1
- Output is always 0
- “Number of functions” definition is useful in proving
completeness property
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Complete Set of Gates
- Complete sets
- A set of gates is complete
- if we can implement any logical function using only the type of
gates in the set
- Some example complete sets
- {AND, OR, NOT} Not a minimal complete set
- {AND, NOT}
- {OR, NOT}
- {NAND}
- {NOR}
- Minimal complete set
- A complete set with no redundant elements.
NAND as a Complete Set
- Proving NAND gate is universal
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Boolean Algebra
Boolean identities
Name AND version OR version
Identity x.1 = x x + 0 = x
Complement x.^ x’ = 0 x + x’ = 1
Commutative x.y = y.x x + y = y + x
Distribution x.^ (y+z) = xy+xz x + (y.^ z) =
(x+y) (x+z)
Idempotent x.x = x x + x = x
Null x.0 = 0 x + 1 = 1
Boolean Algebra (cont’d)
- Boolean identities (cont’d)
Name AND version OR version
Involution x = (x’)’ ---
Absorption x.^ (x+y) = x x + (x.y) = x
Associative x.(y.^ z) = (x.^ y).z x + (y + z) =
(x + y) + z
de Morgan (x
.
y)’ = x’ + y’ (x + y)’ = x’
.
y’
(de Morgan’s law in particular is very useful)
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Majority Function Using Other Gates
- Using NAND gates
- Get an equivalent expression
A B + C D = (A B + C D)’’
A B + C D = ( (A B)’ . (C D)’)’
- Can be generalized
- Example: Majority function
A B + B C + AC = ((A B)’ . (B C)’ . (AC)’)’
Majority Function Using Other Gates (cont'd)
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2-to-1 Multiplexer
(a) Graphical symbol
f
s
w 0
w 1
0 1
(b) Truth table
f
s f
w 0
w 1
(c) Sum-of-products circuit
s
w 0
w 1
(d) Circuit with transmission gates
w 0
w 1 f
s
Source: Brown and Vranesic
4-to-1 Multiplexer
f
s 1 w 0 w 1
00 01
(b) Truth table
w 0 w 1
s 0
w 2 w 3
10 11
0 0 1 1
1 0 1
s 1 f
0
s 0
w 2 w 3
f
(c) Circuit
s 1
w 0
w 1
s 0
w 2
w 3
(a) Graphic symbol
Source: Brown and Vranesic
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Decoders
- Decoder
- n binary inputs
- 2 n^ binary outputs
- Function: decode encoded information
- If enable=1, one output is asserted high, the other outputs are asserted low
- If enable=0, all outputs asserted low
- Often, enable pin is not needed (i.e. the decoder is always enabled)
- Called n-to-2n^ decoder
- Can consider n binary inputs as a single n-bit input
- Can consider 2n^ binary outputs as a single 2n-bit output
- Decoders are often used for RAM/ROM addressing
n-
w 0
n
inputs
Enable En
n
outputs
y
0
w y 2 n^ – 1
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2-to-4 Decoder
0 0 1 1
1 0 1
w 1 y 3
0
w 0
(c) Logic circuit
w 1
w 0
1 1
0
1 1
En
0 0 1
0
0
y 2
0 1 0
0
0
y 1
1 0 0
0
0
y 0
0 0 0
1
0
y 0
y 1
y 2
y 3
En
w 1
En
y 3 w 0 y 2 y 1 y 0
(a) Truth table (b) Graphical symbol
Source: Brown and Vranesic
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Encoders
n
inputs
w 0
y 0
yn – 1
n
outputs
- Encoder
- 2 n^ binary inputs
- n binary outputs
- Function: encodes information into an n-bit code
- Called 2 n-to-n encoder
- Can consider 2n^ binary inputs as a single 2n-bit input
- Can consider n binary output as a single n-bit output
- Encoders only work when exactly one binary input is equal to 1
w 2 n – 1
4-to-2 Encoder
w 3 y 1
y 0
(b) Circuit
w 1
w 0
w 2
w 1
w 0
y 0
w 2
w 3
y 1
(a) Truth table
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Priority Encoders
n
inputs
w
0
w 2 n – 1
y 0
yn – 1
n
outputs
- Priority Encoder
- 2 n^ binary inputs
- n binary outputs
- 1 binary "valid" output
- Function: encodes information into an n-bit code based on priority of inputs
- Called 2 n-to-n priority encoder
- Priority encoder allows for multiple inputs to have a value of '1', as it encodes the input with
the highest priority (MSB = highest priority, LSB = lowest priority)
- "valid" output indicates when priority encoder output is valid
- Priority encoder is more common than an encoder
z "valid" output
4-to-2 Priority Encoder
0 0 1
0 1 0
w 0 y 1
y 0
1 1
0 1
1
1 1
z
1
0
w 1
0 1
0
w 2
0 0 1
0
w 3
0 0 0
0
1
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Multi-Bit Combinational Logic Building
Blocks
Multi-bit 4-to-1 Multiplexer
• When drawing schematics, can draw multi-bit multiplexers
• Example: 4-to-1 (8 bit) multiplexer
• 4 inputs (each 8 bits)
• 1 output (8 bits)
• 2 selection bits
• Can also have multi-bit 2-to-1 muxes, 16-to-1 muxes, etc.
f
s 1 w 0 w 1
00 01
(b) Truth table
w 0 w 1
s 0
w 2 w 3
10 11
0 0 1 1
1 0 1
s 1 f
0
s 0
w 2 w 3
(a) Graphic symbol
8
8
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4-to-1 (8-bit) Multiplexer
f(7)
s 1 00 01
s 0
10 11
f(6)
s 1
00 01
s 0
10 11
f(0)
s 1
00 01
s 0
10 11
w 0 (7) w 1 (7) w 2 (7) w 3 (7)
w 0 (6) w 1 (6) w 2 (6) w 3 (6)
w 0 (0) w 1 (0) w 2 (0) w 3 (0)
A 4-to-1 (8-bit) multiplexer is composed
of eight 4-to-1 (1-bit) multiplexers
f
s 1 w 0 w 1
00 01
s 0
w 2 w 3
10 11 8
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Multi-Bit Ripple-Carry Adder
A 16-bit ripple-carry adder is composed of 16 (1-bit) full adders
Inputs: 16-bit A, 16-bit B, 1-bit carryin (set to zero in the figure below)
Outputs: 16-bit sum R, 1-bit overflow
Other multi-bit adder structures can be studied in ECE 645—Computer Arithmetic
Called a ripple-carry adder because carry ripples from one full-adder to the next.
Critical path is 16 full-adders.
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Combinational Logic Example: ALU (1-bit)
Preliminary ALU design (ALU = arithmetic + logic unit)
Combinational Logic Example: ALU (1-bit)
Optimized
Final design
