Download Exam Questions for Bachelor of Engineering in Applied Electronics Design - December 2005 and more Exams Electrical Engineering in PDF only on Docsity!
Bachelor of Engineering in Applied Electronics Design-Award
NFQ Level 7
December 2005
Electronic Engineering
(Time: 2 Hours)
Answer any 4 questions – 25 marks each. p=10-12^ , n=10-9^ , μ=10- m=10-3^ , k=10^3 , M=10 6
Examiners: Mr. Patrick Collins Mr. Jason Berry Dr Ronan O’Dubhgaill
Q1.
The op-amp used in the circuit in Fig 1 has the following specs: Input offset voltage (VIO) at 25°C = 0.5mV Bias current (I (^) B) at 25°C = 99nA Offset current (I (^) IO) at 25°C = 9nA.
nA C
T
V C I
T
V IO IO = °
AOL at DC = 105dB Open loop gain corner frequency = 5.5Hz. R1 = 10kΩ and R2 = 1kΩ.
(a) If R3 = 0Ω and Vin = 0V then calculate the output error voltage at 25°C – assuming that all errors terms have the same polarity and are at their maximum values. [ 3 marks ] (b) If R1 and R2 are changed to R1 = 100kΩ and R2 = 10kΩ then recalculate the max output error voltage at 25°C. [ 3 marks ] (c) What value of R3 will reduce the max output error voltage? Use the R1, R2 values from part (b). [ 2 marks ] (d) Recalculate the output error voltage in part (b) if this new R3 value is used. [ 3 marks ] (e) Calculate the max error output voltage at 70°C assuming that the new value of R3 is used in the circuit. [ 3 marks ] (f) What is the closed loop bandwidth of the circuit in Fig 1? [ 3 marks ]
(g) If the system has to have a closed loop bandwidth of 125kHz then calculate the value of R required , assuming that R2 = 10kΩ. [ 8 marks ] Vin Vout
R
R
R
Fig 1.
Q2.
a) The diagram in Figure 2 taken from Microchip application note AN687. Prove that the current flowing through the resistor R (^) REF = 1mA.
[ 10 marks ]
Fig 2.
b) Design a circuit to interface an op-amp running off ±15V to a single supply op-amp running off +5V. The dual supply op-amp will produce output voltages to within 1V of each supply rail. The output of the single supply op-amp should be centered about 2.5V with a swing of ±2V. Include a bias current compensating resistor in your answer. [ 15 marks ]
Fig 4.
b) For M1 and M2 above , Vt = 2V and k = 20μA/V^2. Find ID2 if Vdd = 10V and R = 200kΩ. What is the min value of VDS2 for which this current flows? [ 13 marks ]
Q5.
(a) A simple n-well CMOS process needs a minimum of seven layout layers. Name them and give a brief one-line description of the purpose of each one. How is the substrate handled in this system? [ 5 marks ]
(b) What is the difference between a drawn and a derived layer in a layout system? Use the creation of the gate oxide layer of a MOSFET as an example. [ 2 marks ]
(c) The layout used in this question is for a 2μm n-well CMOS scalable architecture. The grid spacing is 1λ = 1μm. The colour coding for the layers is shown below.
For the layout shown in Fig 5 answer the following questions : (1) Identify Q1 and Q2 as NMOS or PMOS devices. Explain how you came to this conclusion. (2) What logic device is implemented in the circuit? (3) What are the W and L dimensions for Q1 and Q2?
For the layout shown in Fig 6 answer the following questions: (1) What logic device is implemented in the circuit? (2) For each region where the polysilicon layer overlaps the active layer , the distance from top to bottom on the diagram is 17μm and the distance from left to right is 6μm. Determine the effective W and L for the top and bottom transistors. [ 10 marks ]
(d) A process has a sheet resistance for polysilicon of 200 Ω/ and a minimum polysilicon dimension of 2μm. It’s CAD system has a resolution of 0.1 μm. Explain how a sheet of polysilicon 2μm by 2 μm can have the same resistance as a sheet of polysilicon 6μm by 6μm. [ 3 marks ]
(e) Using the polysilicon in part (d) as the resistor material , if you require an overall resistance of 1kΩ then what is the minimum sized resistor you can layout? Assuming there is a +/- 0.1μm variation in the width , what is the variation in the final resistance? If the width is tripled to 6μm and you still require a 1kΩ resistor , work out the new L and the variation in the final resistance value. [ 5 marks ]
Fig 6.
