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Cork Institute of Technology
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Bachelor of Engineering in Applied Electronics Design - Award
(NFQ Level 7)
Autumn 2007
Electronic Engineering
(Time: 2 Hours)
Answer any 4 questions – 25 marks each. p=10-12^ , n=10 -9^ , μ=10- m=10 -3^ , k=10^3 , M=10 6
Examiners: Mr. Patrick Collins Mr. David Denieffe Dr Ronan O’Dubhghaill
Q1.
An AD741 has the following specifications: At 25°C the input offset voltage is VIO = 5mV , the input bias current is I (^) B = 100nA and the input offset current is I (^) IO = 9nA. ∆V (^) IO /∆T = 15μV/°C , ∆I (^) B /∆T = 700pA/°C. AOL =106dB. The unity gain bandwidth is UGB = 1.2MHz. The slew rate is SR = 0.5 V/μs.
(a) Draw the frequency response of the magnitude of the open loop gain. Clearly identify the break frequency , the unity gain bandwidth and the slope of the roll-off. [ 4 marks ]
(b) The AD741 is configured as an inverting amplifier. The amplifier is required to have a closed loop bandwidth ( fCL ) of at least 20kHz. If the feedback resistor ( Rf ) = 47kΩ then work out the range of the other resistor ( R1 ). [ 9 marks ]
(c) If R1=1kΩ , then what is the maximum value of a sine wave at 5kHz that can applied before slew rate limiting starts to take place? [ 4 marks ]
(d) If R1=1kΩ then what is the maximum possible output error voltage due to input offset voltage and input bias current effects at 25°C? If a balance resistor is used to reduce the output error voltage then what should this resistor value be and what will be the percentage reduction in the original error voltage? [ 4 marks ]
(e) If the temperature rises to 55°C then what is the new maximum possible output error voltage (with no balance resistor)? [ 4 marks ]
Q2.
(a) A sensor has an output voltage of ±0.3V. This is fed into a single-supply op-amp operating off +5V. The output should produce an output signal of ±1.2V with a DC offset of 2.5V. Assume that because of the frequencies involved , AC coupling is not an option. Design a circuit to do this. (^) [ 12 marks ]
(b) A sensor has an ac output of ± 0.1V with a DC offset of –0.3V. Design a circuit using a single supply op-amp operating off +5V to produce an output signal of ±1.5V with a DC offset of 2.5V. An input of –0.4V should produce an output of 4V and an input of –0.2V is to produce an output of 1V. Assume that ac coupling is not an option. Comment on any assumptions you make. [ 13 marks ]
Q3. (a) Draw the circuit diagram of a Boost converter. Derive an expression for Vout in terms of the input supply voltage ( VS ) and the duty cycle of the switching element. State any assumptions you make. Include the equivalent circuits when the switch is closed and when the switch is open in your derivation. (^) [ 11 marks ]
(b) Design a boost converter that will produce 12V from a 1.5V source. Design for continuous inductor current and an output ripple of <5%. Assume ideal components. Assume that the load is a 600Ω resistor. [ 11 marks ]
(c) Find the maximum current flowing through the inductor in your design in part (b). [ 3 marks ]
Q5.
The layout used in this question is for a 2μm n-well CMOS scalable architecture. The grid spacing is 1λ = 1μm. The colour coding for the layers is shown below.
a) What is a technology file? [ 2 marks ]
b) When would the dimension λ be used in a layout system as opposed to μm? Give one disadvantage and one advantage of a scalable architecture. [ 4 marks ]
c) Explain DRC and LVS. Clearly outline the difference between them. [ 4 marks ]
d) For the layout shown in Figure Q5 answer the following questions : (i) Identify each of the upper and lower transistors as an NMOS or PMOS device. Explain clearly how you came to this conclusion. (ii) What logic device is implemented in the circuit? (iii) What are the W and L dimensions for the upper and lower transistors? [ 6 marks ]
e) A process has a sheet resistance for polysilicon of 150 Ω/ and a minimum polysilicon dimension of 2μm. It’s CAD system has a resolution of 0.1 μm. (i) If you require an overall resistance of 1kΩ then what is the minimum sized resistor you can layout with the closest possible value? (ii) If there is a +/- 0.1μm variation in the width then what is the variation in the final resistance? [ 9 marks ]
FIGURE Q5.
