Download Exam Solutions for ECE 2030 Computer Engineering Fall 2002 - Problem 1 to 4 and more Exams Computer Science in PDF only on Docsity!
4 problems, 4 pages Exam Two Solutions 30 October 2002
Problem 1 (3 parts, 30 points) Numbers and Arithmetic
Part A (9 points) Convert some decimal values (and powers of two) into binary notation:
binary notation decimal notation
10101010 2 + 8 + 32 + 128 = 170
11111.1111 (32-1).(1-.0625)=31.
249 512 trillion (512T)
Part B (9 points) Convert the following hexadecimal values into octal notation:
hexadecimal notation octal notation
4321 0100001100100001 = 41441
14.9 00010100.1001 = 24.
55.AA 01010101.10101010 = 125.
Part C (12 points) For each problem below, (a) compute the operations using the rules of arithmetic, (b) indicate whether an error occurs assuming all numbers are expressed using a four bit two’s complement representation, and (c) indicate whether an error occurs assuming all numbers are expressed using a four bit unsigned representation.
result
signed error?
NO NO NO NO
unsigned error?
NO YES NO YES
4 problems, 4 pages Exam Two Solutions 30 October 2002
Problem 2 (3 parts, 27 points) Storage
Part A (9 points) For the circuit below, complete the truth table describing its behavior. Then label the status of each row from the following choices: SET, RESET, HOLD, META-STABLE.
A B Out status
0 0 Qo HOLD 1 0 0 RESET 0 1 1 SET
A
B
Out
1 1 0 METASTABLE
Part B (9 points) Now implement a transparent latch using this circuit plus additional basic gates (AND, OR, NAND, NOR, and NOT). Label inputs IN and EN. Label output OUT. Do not attempt to employ mixed logic notation.
IN OUT
EN
Part C (9 points) Assume the following signals are applied to a register with write enable. Draw the output signal Out. Draw a vertical line where In is sampled. Assume Out starts at zero.
WE
In
Out
4 problems, 4 pages Exam Two Solutions 30 October 2002
Problem 4 (3 parts, 22 points) Pass Gate Fun
Part A (6 points) For the pass gate symbol shown on the left below, draw its implementation on the right. Be sure that the named terminals (A, B, C, and D) on the right correspond to the icon terminals on the left.
A
B
C
D
A
B
C
D
Part B (8 points) Implement a 1 to 2 demultiplexer using only pass gates and inverters. Label all inputs (IN, S) and outputs (O 0 , O 1 ).
Out
In
Select
Out
Part C (8 points) Using the 1 to 2 demux implemented in part B (in icon form), implement a 1 to 4 demux. Label all inputs (IN, S 0 , S 1 ) and outputs (O 0 , O 1 , O 2 , O 3 ).
IN
OUT 0
S
1 to 2 OUT 1
IN
OUT 0
S
1 to 2 OUT 1
IN
OUT 0
S
1 to 2 OUT 1
IN
OUT 0
OUT 1
OUT 2
OUT 3
S 1 S 0
