Download Exam Solutions for ECE 2030 J - Computer Engineering - Fall 2002 - Problem 1 to 4 and more Exams Computer Science in PDF only on Docsity!
4 problems, 7 pages Exam Two Solutions 29 October 2002
Problem 1 (6 parts, 35 points) Numbers and Arithmetic
Part A (4 points) Convert these binary values (and powers of two) into decimal notation:
binary notation decimal notation 101001.101 41.
239 512Billion
Part B (2 points) Convert this octal value into hexidecimal notation:
octal notation hexadecimal notation 5124.64 0xA54.D
Part C (15 points) For each problem below, (a) compute the addition or subtraction using the rules of arithmetic (note that the third problem is a subtraction) , (b) indicate whether an error occurs assuming all numbers are expressed using a four bit two’s complement representation, and (c) indicate whether an error occurs assuming all numbers are expressed using a four bit unsigned representation.
result 0 0 0 0^ 0 1 1 1^ 0 1 1 1
signed error? No Yes No
unsigned error?
Yes Yes Yes
Part D (4 points) What is the minimum number of bits needed to represent the following decimal integers in a signed two’s complement integer representation?
a) 128: 9 bits.
b) negative thirty-two: 6 bits.
4 problems, 7 pages Exam Two Solutions 29 October 2002
Part E (8 points) The adder below adds two four bit numbers A and B and produces a four bit result S. Add extra digital logic to support subtraction as well as addition. Label inputs X 3 , X 2 ,
X 1 , X 0 , Y 3 , Y 2 , Y 1 , Y 0 , ADD / SUB and outputs Z 3 , Z 2 , Z 1 , Z 0. For this part, do not implement overflow error detection.
A 3 A 2 A 1 A 0 B^3 B^2 B^1 B^0
S 3 S 2 S 1 S 0
Cin
X 3 X 2 X 1 X 0
Y 3 Y 2 Y 1 Y 0
Z 3 Z 2 Z 1 Z 0
ADD/SUB
Cout
Part F (2 points) Now define the behavior for an overflow detection unit for unsigned integers
only. Assume the inputs are carry out Cout , and ADD / SUB. The output Error is 1 for overflow.
ADD / SUB Cout Error 0 0 0 0 1 1 (^1 0) 1 1 1 0
4 problems, 7 pages Exam Two Solutions 29 October 2002
Solution 2:
TE Out Clr
TE Out Clr
TE Out Clr
O 1
O 2
O 3
Ext CE TE Out Clr
O 0
Ext Clr
4 problems, 7 pages Exam Two Solutions 29 October 2002
Problem 3 (3 parts, 25 points) State Machines
Suppose you are a new employee at Trains ’R Us which has developed a new toy train it is ready to market. The train has a remote control box with two switches: one for direction (forward vs. reverse) and one for running the engine (go vs. apply break). The state machine diagram shown below describes the train’s control logic. The inputs to the state machine are the input signals generated by the two switches:
F / R (which is 1 for forward movement and 0 to run backward) and G / B (which is 1 to run the engine and 0 to apply the break). There is one output W. When W=1 , the train’s whistle is blown.
B
stop
move
forward
move
backward
G R
G F
G R / W G F/ W B
B
G F/ W G R/ W
Part A (7 points) You are given the diagram above and asked to write instructions for operating the train. Please answer the following frequently asked questions.
- What does the train do if you reverse direction while the train is moving (i.e., toggle the direction switch)? (List all relevant behaviors of the train.)
The train stops (then continues in the opposite direction).
The train’s whistle blows.
- How can I get the train’s whistle to blow? (List all the ways. Refer only to actions the train operator can take, not to the internal digital design or signals.)
Start the train moving from a standstill.
Switch direction while the train is moving.
Part B (12 points) Fill in the following state table based on the state diagram.
4 problems, 7 pages Exam Two Solutions 29 October 2002
Problem 4 (2 parts, 20 points) Registers and Timing
Part A (4 points) Design a transparent latch using this circuit plus additional basic gates (AND, OR, NAND, NOR, and NOT). Label inputs IN and EN. Label output OUT. Do not attempt to employ mixed logic notation.
IN OUT
EN
Part B (15 points) Consider the register implemented below.
In Out
En
Latch
In Out
En
Latch
mux
out
IN s
WE
OUT
A
phi1 phi
Assume the following signals are applied to your register. Draw the signal at point A (output of the first latch) and the output signal Out. Assume A and Out start at zero.
In
WE
Out
A
