Download VHDL Homework Solutions for Mux Design and more Assignments Electrical and Electronics Engineering in PDF only on Docsity!
EGRE 365 Homework 02 Solutions Work the following problems in chapter 1 of The Designer’s Guide to VHDL. Problem 8. Write the architecture using the provided skeleton. Problem 9. Write two different versions of the architecture using the provided skeleton. Note: for 8 and 9 use type std_logic and turn in a simulation waveform; Use the following skeleton code available on the class web page for problems 8 and 9. Pr oblem 8 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; entity mux is Port ( a : in std_logic; b : in std_logic; sel : in std_logic; z : out std_logic); end mux; architecture behav of mux is begin Put y ou r code her e! end behav; ENTITY tb IS END tb; ARCHITECTURE test OF tb IS signal a, b, sel: std_logic := '0'; signal z_out: std_logic; BEGIN U1: entity work.mux(behav) port map (a, b, sel, z_out); sel <= not sel after 10 ns; a <= not a when sel'event and sel = '0'; b <= not b when a'event and a = '0'; END TEST;
ANSWE R f or pr oble m 8 architecture Bad of mux is begin pr ocess( sel ) be gin if sel = '0 ' then z <= a; else z <= b; end if ; end pr ocess; end B ad; architecture Good of mux is begin pr ocess( sel , a, b) be gin if sel = '0 ' then z <= a; else z <= b; end if ; end pr ocess; end Good; architecture Better of mux is begin z <= a when sel = '0 ' else b; end Better;
architecture Not_struc_2 of mux_4 is begin z0 <= a0 when sel = '0' else b0; z1 <= a1 when sel = '0' else b1; z2 <= a2 when sel = '0' else b2; z3 <= a3 when sel = '0' else b3; end Not_struc_2; architecture struc of mux_4 is begin Put y ou r code her e! U0 : enti ty wor k. mux (bett er) por t ma p(a0 , b0, sel, z0 ); U1 : enti ty wor k. mux (bett er) por t ma p(a1 , b1, sel, z1 ); U2 : enti ty wor k. mux (bett er) por t ma p(a2 , b2, sel, z2 ); U3 : enti ty wor k. mux (bett er) por t ma p(a3 , b3, sel, z3 ); end struc; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; entity mux_4a is Port ( a : in unsigned(3 downto 0); b : in unsigned(3 downto 0); sel : in std_logic; z : out unsigned(3 downto 0) ); end mux_4a; architecture Not_struc of mux_4a is begin Put one l ine o f code her e!
z <= a w hen se l = ' 0' else b; end Not_struc;
Tes t Ben ch library IEEE; -- Make IEEE lib visiable use IEEE.std_logic_1164.all; -- Select package std_logic_ use IEEE.numeric_std.ALL; ENTITY tb IS END tb; ARCHITECTURE test OF tb IS signal a : unsigned(3 downto 0) := "0000"; signal b : Unsigned(3 downto 0) := (others => '0'); signal sel: std_logic := '0'; signal z1, z2, z3, z4: unsigned(3 downto 0); BEGIN U1: entity work.mux_4(Not_Struc_1) port map (a0 => a(0), a1 => a(1), a2 => a(2), a3 => a(3), b0 => b(0), b1 => b(1), b2 => b(2), b3 => b(3), z0 => z1(0), z1 => z1(1), z2 => z1(2), z3 => z1(3), sel => sel); U2: entity work.mux_4(Not_Struc_2) port map (a0 => a(0), a1 => a(1), a2 => a(2), a3 => a(3), b0 => b(0), b1 => b(1), b2 => b(2), b3 => b(3), z0 => z2(0), z1 => z2(1), z2 => z2(2), z3 => z2(3), sel => sel); U3: entity work.mux_4a(struc) port map (a, b, sel, z3); U4: entity work.mux_4a(struc_2) port map (a, b, sel, z4); sel <= not sel after 10 ns; process(sel) begin a <= a + 1; b <= not b(0) & b(3 downto 1); end process; END TEST;
