•1
CPE/EE 422/522
Advanced Logic Design
L03
Electrical and Computer Engineering
University of Alabama in Huntsville
03/06/2003 UAH-CPE/EE 422/522 AM 2
Outline
•What we know
–Combinational Networks
•Analysis, Synthesis, Simplification,
Building Blocks, PALs, PLAs, ROMs
–Sequential Networks: Basic Building Blocks
•What we do not know
–Design: Mealy, Moore
–Sequential Network Timing
–Setup and hold times
–Max clock frequency
03/06/2003 UAH-CPE/EE 422/522 AM 3
Sequential Networks
•Have memory (state)
–Present state depends not only on the current input,
but also on all previous inputs (history)
–Future state depends on the current input and state
))t(Q),t(X(F)t(Z=
x1
x2
xn
z1
z2
zm
Z = z1z2... zm
X = x1x2... xn
Q = Q1Q2... Qk
))t(Q),t(X(G)t(Q=
+
Q
Flip-flops are
commonly used as
storage devices:
D-FF, JK-FF, T-FF
03/06/2003 UAH-CPE/EE 422/522 AM 4
Review: Clocked D Flip-Flop with
Rising-edge Trigger
Next state
The next state in response to the rising edge of the
clock is equal to the D input before the rising edge
03/06/2003 UAH-CPE/EE 422/522 AM 5
Review: Clocked JK Flip-Flop
Next state
JK = 00 => no state change occurs
JK = 10 => the flip-flop is set to 1, independent of the current state
JK = 01 => the flip-flop is always reset to 0
JK = 11 => the flip-flop changes the state Q+= Q’
03/06/2003 UAH-CPE/EE 422/522 AM 6
Review: Clocked T Flip-Flop
Next state
T = 1 => the flip-flop changes the state Q+= Q’
T = 0 => no state change
