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2
Some Random Observations
โ Conditions for stabilized voltage source biasing
โ Emitter resistance, RE, is needed.
โ Base voltage source will have finite resistance, RB.
โ needs to be much larger than RB.
โ Small RB - relative to RS - will attenuate input signal.
โ Larger RE permits larger RB, but results in lower gain.
โ Gain = - RC/RE for RE >> re.
โ Split RE with bypassing increases gain.
โ (^) Requires large bypass capacitor.
โ Limiting case - entire RE bypassed: Gain = - gm RC.
โ Simplified rule-of-thumb biasing is adequate.
๎ 1 ๎๎ธ๎ RE
3
Conflicting Bias and Gain Issues
โ (^) Biasing
โ (^) If RB is small relative to , VB andRE determine IE and, ap- proximately, IC. Stable bias => RE large and high gain => RE small. โ (^) Gain โ (^) Want gain magnitude RC/RE to be โlarge.โ This implies a โsmallโ RE.
โ (^) Gain-bias interaction
โ (^) Want RB to be large relative to RS, while still small relative to
. (i.e. choose RB โฅ 10 RS and โฅ 10 RB) โ (^) Want VCG = VCC โ ICRC to be roughly at mid-point between the VCC and the emitter bias voltage, or โ1/3, 1/3, 1/3โ rule. RC determines bias and gain.
๎ 1 ๎๎ธ๎ RE
๎ 1 ๎๎ธ๎ RE
๎ 1 ๎๎ธ๎ RE
Design Step 1 (Choose RB and R E)
Choose an RB >> 10RS :
RBโ 5000 ๎ถ
must be โฅ 10 RB:
REโ
Nearest standard size*: 470
RE= 470 ๎ถ
๎ 1 ๎๎ธ๎ RE
๎ถ
*RCA Lab: http://www.ese.upenn.edu/rca/components/passive/listcomponents.html#resistors
vout
Design Step 2 (Set R C)
RE= 470 ๎ถ
RB= R 1 โฅ R 2 = 5 k ๎ถ
For a gain of about -10 : RC = 10 RE =4.7k ๎ถ
For a gain of -10 , the collector voltage vout swings 1 V maximum, so the collector resistor bias drop could โin principleโ be as little as 1 V.
470
Nearest standard size*:
RC =4.7k ๎ถ
vout
SPEC:^ vsigโ max=0.1V pk
Design Step 4 (Set R 1 and R 2 )
RE= 470 ๎ถ
RB= 5 k ๎ถ
RC =4.7k ๎ถ
Recall:
RB= R 1 โฅ R 2 = R 1
R 2
R 1 ๎ R 2
= 5 k ๎ถ
And: VBG=
R 2 R 1 ๎ R 2
VCC =1.17V
Or:
R 2
R 1 ๎ R 2
VBG
VCC
470
4.7 k vout
Design Step 4 cont. (Set R 1 and R 2 )
R 1 โฅ R 2 = R 1
R 2
R 1 ๎ R 2
= R 1 โ
0.1= 5 k ๎ถ
Substituting:
R 1 = 50 k ๎ถ
Standard size: R 1 = 47 k ๎ถ
R 2
47 k๎ R 2
Finally: =0.
0.9R 2 =0.1๎47k๎โ R 2 = 5222 ๎ถ
Standard size: R 2 =5.1k ๎ถ
470
4.7 k vout
Revised RB : RB= R 1 โฅ R 2 =
๎ 47 k๎5.1k 52.1k
=4.6k ๎ถ
RE= 470 ๎ถ
RB=4.6k ๎ถ
RC =4.7k ๎ถ
NOTE: ๎^1 ๎๎ธ๎^ REโ^47 k^ ๎ถ^ โฅ^10 RB=^46 k^ ๎ถ
Final Design
vout
4.7 k
470
47 k
5.1 k
23.5 uF
Multisim Simulation
20 Hz Gain
1 Khz Gain
Actual | AV | = 9.
Discussion
1. We neglected re. Including the internal emitter resistance,
the simulated gain becomes:
AV=โ
RC
RE๎ r e
- There is some attenuation of the signal voltage at the base. A more accurate calculation of the input attenuation:
vbgโ
Rin Rin๎ RS
= 4200 4250
Rin= RBโฅ r bg =4.2k ๎ถโ vsig=0.988vsig
Multiplying the two quantities: G=โ9.5โ
0.988=โ9.
This fine-tuning of the estimate may be all that not helpful โ since we will be using 5% components to build the circuit!
Close to 9.3!
Common Emitter Amplifier - Current
Source Biasing
- The current mirror sets IE (IC).
- Rb serves no purpose except to provide a path for the base current. IB =.
3. vsig is the signal source.
I E /๎๎ธ๎ 1 ๎
vsig
Bias Setting - Continued
I (^) ref =
VCC ๎ VEEโ0.
Rref
Choose:
I C โ I Eโ I ref = 1 mA
Rref =
10 โ^3
=23.3k ๎ถ
Choose standard size: (RCA Lab Comp List)
Rref = 22 k ๎ถ
I^ VCC^ =^ I^ ref^ Rref^ ๎^ VBE๎^ Qref^ ๎โ^ VEE
ref
Bias Setting - Completed
With the base โgroundedโ and VBE(Qamp) = 0.7 V ( through RB ):
This implies that there is about a 12 V drop to split across RC and VCB. Choose 6 V each.
RC =
VRC
I C
10 โ^3
= 6 k ๎ถ
Choose standard size: (RCA Lab Comp List)
RC =5.6k ๎ถ
5.6 k Ohm
I Bโ 0
Neglect the base current through RB
I (^) bโ 0
VCC = VRC ๎ VCB๎ Qamp๎โ I (^) B RBโ VRC ๎ VCB
Gain Setting - Continued
Choose the nearest standard size resistors for RC and RE.
RE=
RC
Gain check:
ib=
vsig
RS๎๎๎ธ๎ 1 ๎๎ r e๎ RE ๎
vout =โ RC ic=โ RC ๎ธ ib
vout
vsig
RC
r e๎ RE
5.6 k Ohm
Rs
ib
ie
Design for |AV| = 20 :
270
Typical 18 โค |AV| โฅ 22
RE and C E
overall circuit with bias ac circuit
Re ie Ce
