Complete each Design - Computer Engineering - Solved Exam, Exams of Computer Science

Main points of this exam paper are: Complete Each Design, Decoding Decoders, Computer Engineering, Behavior Table, Basic Gates, Decoder Using, Label All Inputs, Inputs and Outputs, Decoders Shown Below, Label the Decoder

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ECE 2030 A 10:00am Computer Engineering Spring 2010
5 problems, 5 pages Final Exam Solutions Cinco de Mayo 2010
Problem 1 (3 parts, 24 points) Decoding Decoders
Part A (6 points) Define a 1 to 2 decoder by completing the behavior table.
IN EN O0 O1
X 0 0 0
0 1 1 0
1 1 0 1
IN
EN
O0
O1
1 to 2
decoder
Part B (8 points) Implement a 1 to 2 decoder using basic gates. Assume only true (non-
complemented) inputs are available. Label all inputs and outputs.
Part C (10 points) Using only the three 1 to 2 decoders shown below, implement a 2 to 4 decoder
with an enable. Label the decoder inputs (IN1, IN0, EN) and outputs (O0, O1, O2, O3).
IN
EN
O0
O1
1 to 2
decoder
IN
EN
O0
O1
1 to 2
decoder
IN
EN
O0
O1
1 to 2
decoder
O0
O1
O2
O3
IN0
IN1
EN
1
pf3
pf4
pf5

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5 problems, 5 pages Final Exam Solutions Cinco de Mayo 2010 Problem 1 (3 parts, 24 points) Decoding Decoders Part A (6 points) Define a 1 to 2 decoder by completing the behavior table. IN EN O0 O X (^0 0 ) (^0 1 1 ) 1 1 0 1 IN EN O O 1 to 2 decoder Part B (8 points) Implement a 1 to 2 decoder using basic gates. Assume only true (non- complemented) inputs are available. Label all inputs and outputs. Part C (10 points) Using only the three 1 to 2 decoders shown below, implement a 2 to 4 decoder with an enable. Label the decoder inputs (IN 1 , IN 0 , EN) and outputs (O0, O1, O2, O3). IN EN

O

O

1 to 2 decoder

IN

EN

O

O

1 to 2 decoder

IN

EN

O

O

1 to 2 decoder

O

O

O

O

IN

IN

EN

5 problems, 5 pages Final Exam Solutions Cinco de Mayo 2010 Problem 2 (4 parts, 30 points) Design Fiesta Complete each design below. Be sure to label all signals. Part A: Implement the following expression using N and P type switches. OutX = AB⋅C ⋅D Part B: Implement the following behavior using only pass gates and inverters. X Y Z Z A 0 Qo Qo A 1 A A Part C: Determine the appropriate expression for this mixed logic design. How many transistors are required? Out = ABCDE

transistors = 8 + 6 + 4 + 4 x 2 = 26T

Part D: Reimplement the design in Part C using only NAND and NOT gates. How many transistors are required?

transistors = 6 + 2 x 4 + 2 x 2 = 18T

5 problems, 5 pages Final Exam Solutions Cinco de Mayo 2010 Problem 4 (4 parts, 36 points) "Math is fun" Part A (9 points) Consider the instruction set architecture below with fields containing zeros. 0000 0000 00 0000 00 0000 00 0000 0000 0000 0000 opcode dest. reg. source 1 reg. immediate value What is the maximum number of opcodes? (^256) What is the number of registers? (^64) What is the range of the signed immediate value? (^) ±128K Part B (9 points) For the eight bit representations below, determine the most positive value and the step size (difference between sequential values). All answers should be expressed in decimal notation. Fractions (e.g., 3/16ths) may be used. Signed representations are two’s complement. representation most positive value step size unsigned integer (8 bits). (0 bits)

signed fixed-point (6 bits). (2 bits)

unsigned fixed-point (0 bits). (8 bits)

Part C (6 points) A 48 bit floating point representation has a 37 bit mantissa field, a 10 bit exponent field, and one sign bit.

What is the largest value that can be represented (closest to infinity)? 2 511

What is the smallest value that can be represented (closest to zero)? 2 -

How many decimal significant figures are supported? 11

Part D (12 points) For each problem below, compute the operations using the rules of arithmetic, and indicate whether an overflow occurs assuming all numbers are expressed using a five bit unsigned fixed-point and five bit two’s complement fixed-point representations.

result 1.110 0.0000 0.1 100.

unsigned error? ■ no □ yes □ no ■ yes ■ no □ yes □ no ■ yes signed error? ■ no □ yes ■ no □ yes ■ no □ yes □ no ■ yes

5 problems, 5 pages Final Exam Solutions Cinco de Mayo 2010 Problem 5 (5 parts, 30 points) Microcode in Reverse The microcode fragment below comes from a color scanner control program that runs on the datapath discussed in class. Unfortunately, don’t care values (X) have been converted to zeros. Assume register zero is a normal register (not hardwired to the value zero). # X Y Z rwe im en im va^ au en -a/s^ lu en lf^ su en st^ ld en st en r/-w^ msel 1 0 0 3 1 1 4000 0 0 1 C 0 0 0 0 0 0 2 3 0 0 1 0 0 0 0 0 0 0 0 1 0 1 1 3 0 0 2 1 1 FF 0 0 1 8 0 0 0 0 0 0 4 0 0 0 1 1 8 0 0 0 0 1 0 0 0 0 0 5 0 0 1 1 1 FF 0 0 1 8 0 0 0 0 0 0 6 1 2 2 1 0 0 1 0 0 0 0 0 0 0 0 0 7 0 0 0 1 1 8 0 0 0 0 1 0 0 0 0 0 8 0 0 1 1 1 FF 0 0 1 8 0 0 0 0 0 0 9 1 2 2 1 0 0 1 0 0 0 0 0 0 0 0 0 10 0 0 0 1 1 8 0 0 0 0 1 0 0 0 0 0 11 0 2 2 1 0 0 1 0 0 0 0 0 0 0 0 0 12 2 0 2 1 1 2 0 0 0 0 1 1 0 0 0 0 13 3 2 0 0 0 0 0 0 0 0 0 0 0 1 0 1 Part A (5 points) Describe the operation that occurs during cycle 2. Be specific. $0 <- mem[0x4000] For the remaining parts, assume $0 = 0x44022118 at the end of cycle 2. Part B (5 points) What is the value of register 0 at the completion of cycle 7 (in hexadecimal). 0x Part C (5 points) What is the value of register 2 at the completion of cycle 9 (in hexadecimal). 0x3B Part D (5 points) What is the value of register 2 at the completion of cycle 12 (in hexadecimal). 0x1F Part E (10 points) Describe the operation of this microcode fragment. Be specific. Four packed eight-bit unsigned integers are loaded from memory at 0x4000, unpacked. The average of the four values is computed and stored back to memory at 0x4000.