DMA (DIRECT MEMORY ACCESS)
NEED
- Peripheral devices manage the memory bus directly and improve
the speed of transfer between peripheral device and memory without the
intervention of CPU.
CPU Bus signals for DMA
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Computer Achitecture and org - Direct Memory Access - Saritha, Study notes of Computer Architecture and Organization
Summary about DMA (DIRECT MEMORY ACCESS), BUS REQUEST, BUS GRANT, DMA TRANSFER MODES, DMA CONTROLLER, DMA TRANSFER.
Typology: Study notes
2010/2011
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DMA (DIRECT MEMORY ACCESS)
NEED
- Peripheral devices manage the memory bus directly and improve
the speed of transfer between peripheral device and memory without the
intervention of CPU.
CPU Bus signals for DMA
Two control signals used to facilitate the DMA transfer:
- BUS REQUEST
- BUS GRANT
BUS REQUEST:
Signal from DMA controller to the CPU requesting to relinquish control of the
buses.
When this input is high CPU stops executing the instruction and places the
address, data, read and write lines in high impedance.
BUS GRANT:
Signal from CPU to DMA controller to the buses are in high impedance state.
DMA takes the control of buses and memory transfer occur without the
intervention of CPU.
At the end of the transfer, bus request line is disabled followed by bus grant
signal disable and CPU returns to its normal operation
DMA CONTROLLER
-DMA controller is similar to an interface and is used to communicate with the CPU
and IO device.
-Communication to the CPU is established by the data and control lines.
-Communication with IO device is established by DMA request and Acknowledge.
-when BG = 0 , CPU communicate with DMA register through data bus to read or
write to DMA registers.
-When BG =1, CPU relinquished the buses and the DMA can communicate directly
with memory by specifying address in the address bus and enabling read/write
control signals.
-DMA controller consists of address, word count and control register.
Address Register: contains address to specify the desired location in memory and is
incremented after each word is transferred to memory.
Word Count Register: holds number of words to be transferred and decremented
after each transfer and tested for zero.
Control Register: specifies the mode of transfer.
DMA TRANSFER
DMA has its own address, which activates the DS and RS lines.
CPU initializes the DMA through the data bus.
When peripheral device sends a DMA request, DMA controller activates BR,
informing CPU to relinquish the buses. CPU responds by enabling BG.
DMA transfers the value of address register in to address bus and enables DMA
Acknowledge.
Peripheral devices transfers the word in to data bus (write) or receives a word
(read).
After each word is transferred, DMA increments the address register and
decrements its word count register.
If the word count doesn’t reach zero, DMA checks the request line from peripheral
devices.
If the peripheral speed is slow, the DMA request line may come somewhat later.
In this case DMA disables the BR line to CPU, so that CPU continues to execute
its program.
Word count reaches zero, DMA stops transfer and removes BR to CPU.