Memory Addressing in Computer Architecture: MIPS Operand Sizes, Alignment, Byte Ordering, , Slides of Computer Architecture and Organization

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Lecture 03- ISA Memory

Instructions

EE

Computer Architecture

Memory Addressing

 (^) How do we specify memory addresses?  (^) This issue is independent of type of ISA (they all need to address memory)  (^) We need to specify  (^) (1) Operand sizes  (^) (2) Address alignment  (^) (3) Byte ordering for multi-byte operands  (^) (4) Addressing Modes

Alignment

 (^) For multi-byte memory operands  An aligned address for an n-byte operand is an address that is a multiple of n  (^) Word-aligned: 0, 4, 8, 12, etc.  (^) An ISA can require alignment of operands  (^) MIPS: all memory operands must be aligned

More Notes about Memory

Alignment

Aligned

Not

Aligned

MIPS requires that all words start at byte addresses that are multiples of 4 bytes

• (^) Called Alignment: objects fall on address that is multiple of their size. 0, 4, 8, or C hex Last hex digit of address is: 1, 5, 9, or D hex 2, 6, A, or E hex 3, 7, B, or F hex

Another view of Endianness

No, we’re not making this up.  at word address 100 (assume a 4-byte word) long a = 11223344;  (^) big-endian (MSB at word address) layout 100 101 102 103 100 11 22 33 44  (^) little-endian (LSB at word address) layout 103 102 101 100 11 22 33 44 100

Addressing Modes

 (^) What is the location of an operand?  Three basic possibilities  (^) Register: operand is in a register  (^) Register number encoded in the instruction  (^) Immediate: operand is a constant  (^) Constant encoded in the instruction  (^) Memory: operand is in memory  (^) Many address modes possibilities

Load from Memory

Instruction



lw register, constant (register)



Memory address = constant +

register



Memory address = offset + Base

Register



lw $s1, 4($s2)



C code: g = h + A[8];



MIPs code: lw $t0, 32($s3)

add $s1, $s2, $t

Store to Memory Instruction



sw register, constant (register)



Memory address = constant +

register



Memory address = offset + Base

Register



sw $s1, 4($s2)



C code: A[12] = h + A[8];



MIPs code: lw $t0, 32($s3)

add $t0, $s2, $t

Pointers v. Values

Key Concept: A register can hold any 32-bit value. That value can be a (signed) int, an unsigned int, a pointer (memory address), and so on If you write add $t2,$t1,$t0 then $t0 and $t1 better contain values If you write lw $t2,0($t0) then $t better contain a pointer Don’t mix these up!

14

Instruction Format

MIP Instructions are 32-bit

Field: Segment of instruction

Opcode (operation code) field: 6

bits

rs (register source) field: 5 bits

rt (register source) field: 5 bits

rd (register destination) field: 5

bits

shamt (shift amount) field: 5

bits

Instruction Format



Should all MIPS instructions be of

the same format?



lw $t0, 32($s3)



Could specify constant using the

5-bit rt field?



Design Principle 3:

Good Design demands good

compromises

MIP Instruction Formats



R-format



I-format

used by data transfer instructions

Opcode 6-bit

rs 5-bit

rt 5-bit

address 16-bit

+/- 2^15 bytes or 2^13 words

Instruction Format

Instruction Format op rs rt rd shamt funct add R 0 reg reg reg 0 32 sub R 0 reg reg reg 0 34 lw I 35 reg reg address sw I 43 reg reg address

Instruction Format

A[300] = h + A[300]; $t1=A, $s2=h lw $t0, 1200($t1) add $t0, $s2, $t sw $t0, 1200($t1) op rs rt rd shamt funct 100011 01001 01000 0000 0100 1011 0000 000000 10010 01000 01000 00000 100000 101011 01001 01000 0000 0100 1011 0000