MIPS ISA and Organization: Lecture 05, Slides of Computer Architecture and Organization

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Lecture 05- MIPS ISA

EE

Computer Architecture

Reading Assignment

Text Book

Chapter # 2

 3 rd^ Edition

MIPS ISA So Far

Category Instr Op Code Example Meaning Arithmetic (R & I format) add 0 and 32 add $s1, $s2, $s3 $s1 = $s2 + $s subtract 0 and 34 sub $s1, $s2, $s3 $s1 = $s2 - $s add immediate 8 addi $s1, $s2, 6 $s1 = $s2 + 6 or immediate 13 ori $s1, $s2, 6 $s1 = $s2 v 6 Data Transfer (I format) load word 35 lw $s1, 24($s2) $s1 = Memory($s2+24) store word 43 sw $s1, 24($s2) Memory($s2+24) = $s load byte 32 lb $s1, 25($s2) $s1 = Memory($s2+25) store byte 40 sb $s1, 25($s2) Memory($s2+25) = $s load upper imm 15 lui $s1, 6 $s1 = 6 * 2^16 Cond. Branch (I & R format) br on equal 4 beq $s1, $s2, L if ($s1==$s2) go to L br on not equal 5 bne $s1, $s2, L if ($s1 !=$s2) go to L set on less than 0 and 42 slt $s1, $s2, $s3 if ($s2<$s3) $s1=1 else $s1= set on less than immediate 10 slti $s1, $s2, 6 if ($s2<6) $s1=1 else $s1= Uncond. Jump (J & R format) jump 2 j 2500 go to 10000 jump register 0 and 8 jr $t1 go to $t jump and link 3 jal 2500 go to 10000; $ra=PC+

MIPS Registers

Name Reg. No. Usage Preserved on Call? $zero 0 const. value n.a. $v0 - $v1 2-3 values No $a0 - $a3 4-7 arguments Yes $t0 - $t7 8-15 temporaries No $s0 - $s7 16-23 saved Yes $t8 - $t9 24-25 temporaries No $gp 28 Global pointer Yes $sp 29 Stack pointer Yes $fp 30 Frame Pointer Yes $ra 31 Return address Yes

Review of MIPS Instruction

Addressing Modes

PC-relative addressing –instruction address is

the sum of the PC and a 16-bit constant

contained within the instruction

Pseudo-direct addressing – instruction

address is the 26-bit constant contained

within the instruction concatenated with the

upper 4 bits of the PC

op rs rt offset

Program Counter (PC)

Memory

branch destination instruction

op jump address

Program Counter (PC)

Memory

|| jump destination instruction

MIPS (RISC) Design Principles

Simplicity favors regularity

fixed size instructions – 32-bits

small number of instruction formats

opcode always the first 6 bits

Good design demands good compromises

three instruction formats

Smaller is faster

limited instruction set

limited number of registers in register file

limited number of addressing modes

Make the common case fast

arithmetic operands from the register file

(load-store machine)

8 allow instructions to contain immediate

Compiling C if into MIPS



Final compiled MIPS code:

beq $s3,$s4,True # branch i==j sub $s0,$s1,$s2 # f=g-h(false) j Fin # goto Fin True: add $s0,$s1,$s2 # f=g+h (true) Fin:

Note: Compiler automatically creates labels to

handle decisions (branches). Generally not found in

HLL code.

Exit

i == j?

f=g+h f=g-h

(false)

i != j

(true)

i == j

• Compile by hand

if (i == j) f=g+h;

else f=g-h;

Loops

do{g =g + A[i];

i = i + j;

}while(i != h);

loop: add $t1, $s3, $s

add $t1, $t1, $t

add $t1, $t1, $s

lw $t0, 0($t1)

add $s1, $s1, $t

add $s3, $s3, $s

bne $s3, $s2, loop

g, h, i, j, A

$s1, $s2, $s3, $s4,$s

Example: The C Switch

Statement (1/3)

Choose among four alternatives depending

on whether k has the value 0, 1, 2 or 3.

Compile this C code:

switch (k) {

case 0: f=i+j; break; /* k=0 */

case 1: f=g+h; break; /* k=1 */

case 2: f=g–h; break; /* k=2 */

case 3: f=i–j; break; /* k=3 */

Example: The C Switch

Statement (2/3)

This is complicated, so simplify.

Rewrite it as a chain of if-else statements,

which we already know how to compile:

if(k==0) f=i+j;

else if(k==1) f=g+h;

else if(k==2) f=g–h;

else if(k==3) f=i–j;

Use this mapping:

f:$s0, g:$s1, h:$s2,

i:$s3, j:$s4, k:$s

int leaf_example (int g, int h, int i, int j)  {  int f; f = (g + h) – (i + j); return f; }