Computer Organization Lecture 2: MIPS ISA and Performance, Slides of Computer Science

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Computer Organization

Lecture 2

Review of MIPS ISA and Performance

Overview of Today‟s Lecture

 ISA, Addressing, Format (20 min)

 Administrative Matters (5 min)

 Operations, Branching, Calling conventions (25 min)

 Break (5 min)

 MIPS Details, Performance (25 min)

Instruction Set Architecture:

What Must be Specified?

Instruction

Fetch

Instruction

Decode

Operand

Fetch

Execute

Result

Store

Next

Instruction

 Instruction Format or Encoding

• How is it decoded?

 Location of operands and result

• Where other than memory?
• How many explicit operands?
• How are memory operands located?
• Which can or cannot be in memory?

 Data type and Size

 Operations

• What are supported

 Successor instruction

• Jumps, conditions, branches
• Fetch-decode-execute is implicit!

Basic ISA Classes

Accumulator (1 register):

1 address add A acc  acc + mem[A]

1+x address addx A acc  acc + mem[A + x]

Stack:

0 address add tos  tos + next

General Purpose Register (can be memory/memory):

2 address add A B EA[A]  EA[A] + EA[B]

3 address add A B C EA[A]  EA[B] + EA[C]

Load/Store:

3 address add Ra Rb Rc Ra  Rb + Rc

load Ra Rb Ra  mem[Rb]

store Ra Rb mem[Rb]  Ra

Comparison: Bytes per instruction? Number of Instructions? Cycles per instruction?

Most real machines are hybrids of these:

General Purpose Registers Dominate

 1975-2002 all machines use general purpose registers

 Advantages of registers

• Registers are faster than memory
• Registers are easier for a compiler to use
  • E.g., (AB) – (CD) – (E*F) can do multiplies in any order vs. stack
• Registers can hold variables
  • Memory traffic is reduced, so program is sped up (since registers are faster than memory)
• Code density improves (since register named with fewer bits than memory location)

MIPS I Registers

 Programmable storage

• 2^32 x bytes of memory
• 31 x 32-bit GPRs (R0 = 0)
• 32 x 32-bit FP regs (paired DP)
• HI, LO, PC

r0^0 r ° ° ° r PC lo hi

Addressing Objects: Endianess and Alignment

 Big Endian: address of most significant byte = word

address (xx00 = Big End of word)

• IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA

 Little Endian: address of least significant byte = word

address (xx00 = Little End of word)

• Intel 80x86, DEC Vax, DEC Alpha (Windows NT)

msb lsb

little endian byte 0

big endian byte 0

Alignment: require that objects fall on address

that is multiple of their size.

Aligned

Not

Aligned

Addressing Modes

Addressing mode Example Meaning

Register Add R4,R3 R4 R4+R

Immediate Add R4,#3 R4 R4+

Displacement Add R4,100(R1) R4 R4+Mem[100+R1]

Register indirect Add R4,(R1) R4 R4+Mem[R1]

Indexed / Base Add R3,(R1+R2) R3 R3+Mem[R1+R2]

Direct or absolute Add R1,(1001) R1 R1+Mem[1001]

Memory indirect Add R1,@(R3) R1 R1+Mem[Mem[R3]]

Post-increment Add R1,(R2)+ R1 R1+Mem[R2]; R2 R2+d

Pre-decrement Add R1,–(R2) R2 R2–d; R1 R1+Mem[R2]

Scaled Add R1,100(R2)[R3] R1 R1+Mem[100+R2+R3*d]

Why Post-increment/Pre-decrement? Scaled?

Docsity.com

Displacement Address Size?

° Avg. of 5 SPECint92 programs v. avg. 5 SPECfp92 programs

° 1% of addresses > 16-bits

° 12 - 16 bits of displacement needed

Int. Av g. FP Av g.

Address Bits

Immediate Size?

• 50% to 60% fit within 8 bits

• 75% to 80% fit within 16 bits

Generic Examples of Instruction Format Widths

Variable:

Fixed:

Hybrid:

Instruction Formats

 If code size is most important, use variable length

instructions

 If performance is most important, use fixed length

instructions

 Recent embedded machines (ARM, MIPS) added

optional mode to execute subset of 16-bit wide

instructions (Thumb, MIPS16); per procedure decide

performance or density

 Some architectures actually exploring on-the-fly

decompression for more density.

MIPS Addressing Modes/Instruction Formats

op rs rt rd

immed

register

Register (direct)

op rs rt

register

Base+index

Memory

Immediate op rs rt immed

op rs rt immed

PC

PC-relative

Memory

• All instructions 32 bits wide

• Register Indirect?

Administrative Matters

 CS152 news group: ucb.class.cs

(email cs152@cory with specific questions)

 Slides and handouts available via web:

http://www.cs.berkeley.edu/classes/cs

 Sign up to the cs152-announce mailing list:

• Go to the “Information” page, look under “Course Operation”

 Sections are on Tuesday and Friday:

• Tuesday: Room TBD, 9-11 or 10-
• Friday: 9:00 – 11:00 320 Soda

 Get Cory key card/card access to Cory 119

• Your NT account names are derived from your UNIX “named” accounts: „cs152-yourUNIXname‟