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Randal E. Bryant

Carnegie Mellon University

CS:APP2e

CS:APP Chapter 4

Computer Architecture

Sequential

Implementation

http://csapp.cs.cmu.edu

Y86 Instruction Set #

Byte 0 1 2 3 4 5

pushl rA A (^0) rA 8

jXX Dest (^7) fn Dest

popl rA B (^0) rA 8

call Dest (^8 0) Dest

cmovXX rA, rB (^2) fn rA rB

irmovl V, rB (^3 0 8) rB V

rmmovl rA, D(rB) (^4 0) rA rB D

mrmovl D(rB), rA (^5 0) rA rB D

OPl rA, rB (^6) fn rA rB

ret 9 0

nop 1 0

halt 0 0

rrmovl 7 0

cmovle 7 1

cmovl 7 2

cmove 7 3

cmovne 7 4

cmovge 7 5

cmovg 7 6

Y86 Instruction Set #

Byte 0 1 2 3 4 5

pushl rA A (^0) rA 8

jXX Dest (^7) fn Dest

popl rA B (^0) rA 8

call Dest (^8 0) Dest

rrmovl rA, rB (^2) fn rA rB

irmovl V, rB (^3 0 8) rB V

rmmovl rA, D(rB) (^4 0) rA rB D

mrmovl D(rB), rA (^5 0) rA rB D

OPl rA, rB (^6) fn rA rB

ret 9 0

nop 1 0

halt 0 0

jmp 7 0

jle 7 1

jl 7 2

je 7 3

jne 7 4

jge 7 5

jg 7 6

Building Blocks

Combinational Logic

 Compute Boolean functions of inputs

 Continuously respond to input changes

 Operate on data and implement control

Storage Elements

 Store bits

 Addressable memories

 Non-addressable registers

 Loaded only as clock rises

Register file

A

B

W (^) dstW

srcA

valA

srcB

valB

valW

Clock

A

L

U

fun

A

B

MUX

=

Clock

HCL Operations

 Classify by type of value returned

Boolean Expressions

 Logic Operations

 a && b , a || b , !a

 Word Comparisons

 A == B , A != B , A < B , A <= B , A >= B , A > B

 Set Membership

 A in { B, C, D }

» Same as A == B || A == C || A == D

Word Expressions

 Case expressions

 [ a : A; b : B; c : C ]

 Evaluate test expressions a , b , c , … in sequence

 Return word expression A , B , C , … for first successful test

SEQ Hardware

Structure

State

 Program counter register (PC)

 Condition code register (CC)

 Register File

 Memories

 Access same memory space

 Data: for reading/writing program

data

 Instruction: for reading

instructions

Instruction Flow

 Read instruction at address

specified by PC

 Process through stages

 Update program counter

Instruction memory

Instruction memory increment^ PC

PC increment

CC CC (^) ALUALU

Data memory

Data memory

Fetch

Decode

Execute

Memory

Write back

icode , ifun

rA , rB valC

Register file

Register file

A B (^) M E

Register file

Register file

A B (^) M E

PC

valP

srcA, srcB dstA, dstB

valA, valB

aluA, aluB

Cnd

valE

Addr, Data

valM

PC

valE, valM

newPC

Instruction Decoding

Instruction Format

 Instruction byte icode:ifun

 Optional register byte rA:rB

 Optional constant word valC

(^5 0) rA rB D

icode

ifun

rA

rB

valC

Optional Optional

Executing Arith./Logical Operation

Fetch

 Read 2 bytes

Decode

 Read operand registers

Execute

 Perform operation

 Set condition codes

Memory

 Do nothing

Write back

 Update register

PC Update

 Increment PC by 2

OPl rA , rB 6 fn rA rB

Executing rmmovl

Fetch

 Read 6 bytes

Decode

 Read operand registers

Execute

 Compute effective address

Memory

 Write to memory

Write back

 Do nothing

PC Update

 Increment PC by 6

rmmovl rA , D ( rB) 4 0 rA rB D

Stage Computation: rmmovl

 Use ALU for address computation

rmmovl rA, D(rB)

icode:ifun ← M 1 [PC]

rA:rB ← M 1 [PC+1]

valC ← M 4 [PC+2]

valP ← PC+

Fetch

Read instruction byte

Read register byte

Read displacement D

Compute next PC

valA ← R[rA]

valB ← R[rB]

Decode

Read operand A

Read operand B

valE ← valB + valC

Execute

Compute effective address

Memory M 4 [valE] ← valA Write value to memory

Write

back

PC update PC ← valP Update PC

Stage Computation: popl

 Use ALU to increment stack pointer

 Must update two registers

 Popped value

 New stack pointer

popl rA

icode:ifun ← M 1 [PC]

rA:rB ← M 1 [PC+1]

valP ← PC+

Fetch

Read instruction byte

Read register byte

Compute next PC

valA ← R[ %esp ]

valB ← R [ %esp ]

Decode

Read stack pointer

Read stack pointer

valE ← valB + 4

Execute

Increment stack pointer

Memory valM ← M 4 [valA] Read from stack

R[ %esp ] ← valE

R[rA] ← valM

Write

back

Update stack pointer

Write back result

PC update PC ← valP Update PC

Executing Jumps

Fetch

 Read 5 bytes

 Increment PC by 5

Decode

 Do nothing

Execute

 Determine whether to take

branch based on jump

condition and condition

codes

Memory

 Do nothing

Write back

 Do nothing

PC Update

 Set PC to Dest if branch

taken or to incremented PC

if not branch

jXX Dest 7 fn Dest

fall thru:^ XX^ XX

target:^ XX^ XX

Not taken

Taken

Executing call

Fetch

 Read 5 bytes

 Increment PC by 5

Decode

 Read stack pointer

Execute

 Decrement stack pointer by

Memory

 Write incremented PC to

new value of stack pointer

Write back

 Update stack pointer

PC Update

 Set PC to Dest

call Dest 8 0 Dest

return:^ XX^ XX

target:^ XX^ XX

Stage Computation: call

 Use ALU to decrement stack pointer

 Store incremented PC

call Dest

icode:ifun ← M 1 [PC]

valC ← M 4 [PC+1]

valP ← PC+

Fetch

Read instruction byte

Read destination address

Compute return point

valB ← R[ %esp ]

Decode

Read stack pointer

valE ← valB + –

Execute

Decrement stack pointer

Memory M 4 [valE] ← valP Write return value on stack

Write R[ %esp ] ← valE

back

Update stack pointer

PC update PC ← valC Set PC to destination