Computer Organisation - How to design a processor, Study notes of Computer Architecture and Organization

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How to design a processor?

Structure – The CPU

Computer

Arithmetic

and

Logic Unit

Control

Unit

Internal CPU

Interconnection

Registers

CPU

I/O

Memory

System

Bus

CPU

BASIC COMPUTER REGISTERS

List of BC Registers

DR 16 Data Register Holds memory operand

AR 12 Address Register Holds address for memory

AC 16 Accumulator Processor register

IR 16 Instruction Register Holds instruction code

PC 12 Program Counter Holds address of instruction

TR 16 Temporary Register Holds temporary data

INPR 8 Input Register Holds input character

OUTR 8 Output Register Holds output character

Registers

Registers in the Basic Computer

PC

IR

TR

OUTR

DR

AC

AR

INPR

Memory

4096 x 16

CPU

Registers

• Registers

▫A Binary counter with load and clear

control

 Refer Chapter 2 – figure 2-

• (^) Memory unit

▫4096*16 = 8kb

▫Realized using Block RAM available on

FPGA

Register - 4 bit

COMMON DATA BUS SYSTEM

Registers

S

S

S

Bus

Memory unit

4096 x 16

LD INR CLR

Address

Write Read

AR

LD INR CLR

PC

LD INR CLR

DR

LD INR CLR

ALU AC

E

INPR

IR

LD

LD INR CLR

TR

OUTR

LD

Clock

16-bit common bus

7 1 2 3 4 5 6

Register and bus

Control Unit

Hardwired

Structure – The Control unit

CPU

Control

Memory

Control Unit

Registers and

Decoders

Sequencing

Logic

Control

Unit

ALU

Registers

Internal

Bus

Control Unit

TIMING AND CONTROL

Control unit of Basic Computer

Timing and control

Instruction register (IR)

3 x 8

decoder

7 6 5 4 3 2 1 0

I

D

15 14.... 2 1 0

4 x 16

decoder

4-bit

sequence

counter

(SC)

Increment (INR)

Clear (CLR)

Clock

Other inputs

Control

signals

D

T

T

Combinational

Control

logic

Register-Reference

CLA

CLE

CMA

CME

CIR

CIL

INC

SPA

SNA

SZA

SZE

HLT

Input-Output

INP

OUT

SKI

SKO

ION

IOF

D 7

IT 3

= r

IR(i) = B i

r:

rB 11

:

rB 10

:

rB 9

:

rB 8

:

rB 7

:

rB 6

:

rB 5

:

rB 4

:

rB 3

:

rB 2

:

rB 1

:

rB 0

:

D 7

IT 3

= p

IR(i) = B i

p:

pB 11

:

pB 10

:

pB 9

:

pB 8

:

(Common to all register-reference instr)

(i = 0,1,2, ..., 11)

SC  0

AC  0

E  0

AC  AC

E  E

AC  shr AC, AC(15)  E, E  AC(0)

AC  shl AC, AC(0)  E, E  AC(15)

AC  AC + 1

If(AC(15) =0) then (PC  PC + 1)

If(AC(15) =1) then (PC  PC + 1)

If(AC = 0) then (PC  PC + 1)

If(E=0) then (PC  PC + 1)

S  0

(Common to all input-output instructions)

(i = 6,7,8,9,10,11)

SC  0

AC(0-7)  INPR, FGI  0

OUTR  AC(0-7), FGO  0

If(FGI=1) then (PC  PC + 1)

If(FGO=1) then (PC  PC + 1)

IEN  1

IEN  0

Description

COMPLETE COMPUTER DESCRIPTION

Microoperations

Control Logic Gates

• Input Controls of the eight registers ( AR,

PC, DR, IR, TR, OUTR, INPR, and SC )

▫ LD, INR and CLR

• Read and Write Controls of memory
• Set, Clear, or Complement Controls of the

flip-flops( I, S, E, R, IEN, FGI, and FGO )

• S 2

, S

1

, S

0

controls to select a register for

the bus’s

• AC, and Adder and Logic circuit controls

CONTROL OF REGISTERS AND MEMORY

Scan all of the register transfer statements that change the content of DR:

LD(DR) = D

0

T

4

+ D

1

T

4

+ D

2

T

4

+ D

6

T

4

INR(DR) = D

6

T

5

Data Register; DR

D

0

T

4

: DR  M[AR] LD(DR)

D

1

T

4

: DR  M[AR] LD(DR)

D

2

T

4

: DR  M[AR] LD(DR))

D

6

T

4

: DR  M[AR] LD(DR)

D

6

T

5

: DR  DR + 1 INR(DR)

Design of Basic Computer

CONTROL OF REGISTERS AND MEMORY

Scan all of the register transfer statements that change the content of PC:

Program Counter :PC

D

4

T

4

: PC  AR LD(PC)

D

5

T

5

: PC  AR LD(PC)

RT

1

: PC  0 CLR(PC)

RT

1

: PC  PC + 1 INR(PC)

RT

2

: PC  PC + 1 INR(PC)

D

6

T

6

and DR=0: PC  PC + 1 INR(PC)

rB 4

and AC(15): PC  PC + 1 INR(PC)

rB 3

and AC(15): PC  PC + 1 INR(PC)

rB 2

and AC=0: PC  PC + 1 INR(PC)

rB 1

and E’: PC  PC + 1 INR(PC)

pB 9

and FGI: PC  PC + 1 INR(PC)

pB 8

and FGO: PC  PC + 1 INR(PC)

Design of Basic Computer