Computer Organisation - MICROPROGRAMMED CONTROL and PDF CPU Architecture, Study notes of Computer Architecture and Organization

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MICROPROGRAMMED

CONTROL

COMPARISON OF CONTROL UNIT IMPLEMENTATIONS

Implementation of Control Unit

Control Unit Implementation Combinational Logic Circuits (Hard-wired) Microprogramed

I R Status F/Fs

Control Data

Combinational

Logic Circuits

Control

Points

CPU

Memory

Timing State

Ins. Cycle State

Control Unit's State

Status F/Fs

Control Data

Next Address

Generation

Logic

C

S

A

R

Control

Storage

(-program

memory)

M e m o r y

I R

C

S

D

R

C

P

s

D CPU

}

TERMINOLOGY Microprogram

• Program stored in memory that generates all the control signals required to execute the instruction set correctly
• Consists of microinstructions Microinstruction
• Contains a control word and a sequencing word Control Word - All the control information required for one clock cycle Sequencing Word - Information needed to decide the next microinstruction address
• Vocabulary to write a Microprogram Control Memory(Control Storage: CS)
• Storage in the Microprogramed control unit to store the Microprogram

TERMINOLOGY Sequencer (Microprogram Sequencer) A Microprogram Control Unit that determines the Microinstruction Address to be executed in the next clock cycle

CONDITIONAL BRANCH Unconditional Branch Fixing the value of one status bit at the input of the multiplexer to 1

Sequencing

Conditional Branch If Condition is true, then Branch (address from the next address field of the current microinstruction) else Fall Through Conditions to Test: O(overflow), N(negative), Z(zero), C(carry), etc.

MAPPING OF INSTRUCTIONS

Sequencing

ADD Routine

AND Routine

LDA Routine

STA Routine

BUN Routine

Control

Storage

OP-codes of Instructions ADD AND LDA STA BUN 0000 0001 0010 0011 0100 . . . Direct Mapping

Address

Mapping Bits

10 xxxx 010

ADD Routine

Address

AND Routine

LDA Routine

STA Routine

BUN Routine

MACHINE INSTRUCTION FORMAT Microinstruction Format

Microprogram

EA is the effective address Symbol OP-code Description ADD 0000 AC AC + M[EA]AC + M[EA] BRANCH 0001 if (AC < 0) then (PC AC + M[EA] EA) STORE 0010 M[EA] AC + M[EA] AC EXCHANGE 0011 AC AC + M[EA] M[EA], M[EA] AC + M[EA] AC Machine instruction format I Opcode

Address

Sample machine instructions F1 F2 F3 CD BR AD

F1, F2, F3: Microoperation fields CD: Condition for branching BR: Branch field AD: Address field

MICROINSTRUCTION FIELD DESCRIPTIONS - F1,F2,F F1 Microoperation Symbol 000 None NOP 001 AC  AC + DR ADD 010 AC  0 CLRAC 011 AC  AC + 1 INCAC 100 AC  DR DRTAC 101 AR  DR(0-10) DRTAR 110 AR  PC PCTAR 111 M[AR]  DR WRITE

Microprogram

F2 Microoperation Symbol 000 None NOP 001 AC  AC - DR SUB 010 AC  AC  DR OR 011 AC  AC  DR AND 100 DR  M[AR] READ 101 DR  AC ACTDR 110 DR  DR + 1 INCDR 111 DR(0-10)  PC PCTDR F3 Microoperation Symbol 000 None NOP 001 AC  AC  DR XOR 010 AC  AC’ COM 011 AC  shl AC SHL 100 AC  shr AC SHR 101 PC  PC + 1 INCPC 110 PC  AR ARTPC 111 Reserved

SYMBOLIC MICROINSTRUCTIONS

• (^) Symbols are used in microinstructions as in assembly language
• (^) A symbolic Microprogram can be translated into its binary equivalent by a Microprogram assembler. Sample Format five fields: label; micro-ops; CD; BR; AD Label: may be empty or may specify a symbolic address terminated with a colon Micro-ops: consists of one, two, or three symbols separated by commas CD: one of {U, I, S, Z}, where U: Unconditional Branch I: Indirect address bit S: Sign of AC Z: Zero value in AC BR: one of {JMP, CALL, RET, MAP} AD: one of {Symbolic address, NEXT, empty}

Microprogram

SYMBOLIC MICROPROGRAM - FETCH ROUTINE

AR PC

DR  M[AR], PC  PC + 1

AR  DR(0-10), CAR(2-5)  DR(11-14), CAR(0,1,6)  0

Symbolic Microprogram for the fetch cycle:

ORG 64

PCTAR U JMP NEXT

READ, INCPC U JMP NEXT

DRTAR U MAP

FETCH:

Binary equivalents translated by an assembler 1000000 110 000 000 00 00 1000001 1000001 000 100 101 00 00 1000010 1000010 101 000 000 00 11 0000000 Binary address F1 F2 F3 CD BR AD

Microprogram

During FETCH, Read an instruction from memory and decode the instruction and update PC Sequence of microoperations in the fetch cycle:

Microprogram

Address Binary Microinstruction Micro Routine Decimal Binary F1 F2 F3 CD BR AD ADD 0 0000000 000 000 000 01 01 1000011 1 0000001 000 100 000 00 00 0000010 2 0000010 001 000 000 00 00 1000000 3 0000011 000 000 000 00 00 1000000 BRANCH 4 0000100 000 000 000 10 00 0000110 5 0000101 000 000 000 00 00 1000000 6 0000110 000 000 000 01 01 1000011 7 0000111 000 000 110 00 00 1000000 STORE 8 0001000 000 000 000 01 01 1000011 9 0001001 000 101 000 00 00 0001010 10 0001010 111 000 000 00 00 1000000 11 0001011 000 000 000 00 00 1000000 EXCHANGE 12 0001100 000 000 000 01 01 1000011 13 0001101 001 000 000 00 00 0001110 14 0001110 100 101 000 00 00 0001111 BINARY MICROPROGRAM

Hardwired Vs Micro programmed

• (^) When using a Hardwired approach a faster optimized CPU can be designed
• (^) But it is difficult to design processor with large and complex instruction set. ▫It become difficult to properly lay out the logic so that related circuits are close to one another in the two dimension space of the chip
• (^) A hardwired unit is difficult to modify

Hardwired Vs Micro programmed

• (^) Very complex instruction that consist of several different operations can be designed using Microprogrammed approach.
• (^) Disadvantage is speed of the Microprogrammed processor is tied to internal microcode execution unit. Microcode execution unit is usually quite fast but it need to fetch data from microcode ROM. If memory technology is slower than execution logic, ROM will slow down the processor

Hardwired Vs Micro programmed

• (^) Which approach is better for CPU Design? ▫Intel used microcode approach for 8086 and still uses(till IA32) combination of microcode and hardwired approach for its processors ▫Most modern non-x86 processors use random logic