Memory Organization: A Comprehensive Guide to Memory Hierarchy, Cache, and Virtual Memory, Study Guides, Projects, Research of Organization Theory and Design

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Overview

➢ Memory Hierarchy

➢ Main Memory

➢ Auxiliary Memory

➢ Associative Memory

➢ Cache Memory

➢ Virtual Memory

Memory Hierarchy

Magnetic

tapes

Magnetic

disks

I/O

processor

CPU

Main

memory

Cache

memory

Register

Cache

Main Memory

Magnetic Disk

Magnetic Tape

Memory Hierarchy is to obtain the highest possible access speed while

minimizing the total cost of the memory system

Memory Address Map

Address space assignment to each memory chip

Example: 512 bytes RAM and 512 bytes ROM

RAM 1

RAM 2

RAM 3

RAM 4

ROM

0000 - 007F

0080 - 00FF

0100 - 017F

0180 - 01FF

0200 - 03FF

Component

Hexa

address

0 0 0 x x x x x x x

0 0 1 x x x x x x x

0 1 0 x x x x x x x

0 1 1 x x x x x x x

1 x x x x x x x x x

Address bus

Memory Connection to CPU

- RAM and ROM chips are connected to a CPU through the data and

address buses

- - The low-order lines in the address bus select the byte within the

chips and other lines in the address bus select a particular chip

through its chip select inputs

Connection of Memory to CPU

CS

CS

RD

WR

AD

128 x 8

RAM 1

CS

CS

RD

WR

AD

128 x 8

RAM 2

CS

CS

RD

WR

AD

128 x 8

RAM 3

CS

CS

RD

WR

AD

128 x 8

RAM 4

Decoder

3 2 1 0

16 - 11 10 9 8 7 - 1 RD WR

Address bus

Data bus

CPU

CS

CS

512 x 8

ROM

AD

1 - 7

9

8

Data

Data

Data

Data

Data

Auxiliary Memory

Information Organization on Magnetic Tapes

EOF

IRG

block 1 block 2

block 3

block 1

block 2

block 3

R

R2 R3 R

R

R

R

R3 R

R5 R

file i

EOF

Organization of Disk Hardware

Track

Moving Head Disk Fixed Head Disk

Devices that

provide backup

storage are

called auxiliary

memory. E.g.

Magnetic disks

and tapes.

Associative Memory

Argument register(A)

Key register (K)

Associative memory

array and logic

m words

n bits per word

Match

register

Input

Read

Write

M

- Accessed by the content of the data rather than by an address

- Also called Content Addressable Memory (CAM)

Hardware Organization

Match Logic

F'

i

F

i

K

1

A

1

F'

i

F

i

K

2

A

2

F'

in

F

in

K

n

A

n

M

i

Cache Memory

Locality of Reference

- The references to memory at any given time interval tend to be confined

within a localized areas

- This area contains a set of information and the membership changes

gradually as time goes by

- Temporal Locality

The information which will be used in near future is likely to be in use

already( e.g. Reuse of information in loops)

- Spatial Locality

If a word is accessed, adjacent(near) words are likely accessed soon

(e.g. Related data items (arrays) are usually stored together;

instructions are executed sequentially)

Cache

- The property of Locality of Reference makes the cache memory systems work

- Cache is a fast small capacity memory that should hold those information

which are most likely to be accessed

Main memory

Cache memory

CPU

Memory and Cache Mapping – (Associative Mapping)

Associative mapping

Direct mapping

Set-associative mapping

Associative Mapping

Mapping Function

Specification of correspondence between main memory blocks and cache

blocks

- Any block location in Cache can store any block in memory

- > Most flexible

- Mapping Table is implemented in an associative memory

- > Fast, very Expensive

- Mapping Table

Stores both address and the content of the memory word

address (15 bits)

Argument register

Address Data

CAM

Cache Mapping – direct mapping

• Each memory block has only one place to load in Cache
• Mapping Table is made of RAM instead of CAM
• n-bit memory address consists of 2 parts; k bits of Index field and n-k bits of Tag field
• n-bit addresses are used to access main memory and k-bit Index is used to access the

Cache

Addressing Relationships

Direct Mapping Cache Organization

Memory

address Memory data

Index

address

Tag Data

Cache memory

Tag(6) Index(9)

32K x 12

Main memory

Address = 15 bits

Data = 12 bits

512 x 12

Cache memory

Address = 9 bits

Data = 12 bits

n - k k

Cache Mapping – Set Associative Mapping

Set Associative Mapping Cache with set size of two

- Each memory block has a set of locations in the Cache to load

Index Tag Data

Tag Data

Cache Write

Write Through

When writing into memory

If Hit, both Cache and memory is written in parallel

If Miss, Memory is written

For a read miss, missing block may be overloaded onto a cache

block

Memory is always updated

- > Important when CPU and DMA I/O are both executing

Slow, due to the memory access time

Write-Back (Copy-Back)

When writing into memory

If Hit, only Cache is written

If Miss, missing block is brought to Cache and write into Cache

For a read miss, candidate block must be written back to the

memory

Memory is not up-to-date, i.e., the same item in Cache and memory

may have different value

Virtual memory to form a large range of contiguous addresses.

Address Mapping

Organization of memory Mapping Table in a paged system

Address Space and Memory Space are each divided into fixed size group

of words called blocks or pages

1K words group

Page 0

Page 1

Page 2

Page 3

Page 4

Page 5

Page 6

Page 7

Block 3

Block 2

Block 1

Block 0 Address space

N = 8K = 2

13

Memory space

M = 4K = 2

12

Block 0

Block 1

Block 2

Block 3

MBR

Table

address

Presence

bit

Page no. Line number

Virtual address

Main memory

address register

Memory page table

Main memory