Download Problems Set with Solution for Computer Organization | EE 3755 and more Assignments Electrical and Electronics Engineering in PDF only on Docsity!
EE 3755 Homework 1 Due: Oct. 20.
Estimated time to solve: Prob. 1 30 minutes. Prob. 2 30 minutes. Prob. 3 1 hours. Prob. 4 1 hours. Total 3 hours.
How to submit?
// No hard copy.
// Name your program file as hw1.v
// Name your script file as hw1.txt
// Leave your program file(hw1.v) and
// your script file(hw1.txt) on the class account.
Finish your program file(hw1,v) first, then do the followings: Use “script hw1.txt “ command // To take a snap shot of your program. If you don’t know // script command, look at the handout. Use “cat hw1.v” command // To display contents of your program. Use “ncverilog hw1.v” //To run your program. then stop the script. Example) SUN>script hw1.txt SUN>cat hw1.v SUN>ncverilog hw1.v SUN> ( stop script by pressing CTRL-D)
Fig.1 Half-Adder.
Fig.2 Full Adder by using two half-adders.
Copy the homework template into your account and name it hw1.v. Simulate the welcome module in the homework template.
Problem 1: Complete module half_adder_ex (in the homework template) so that it is an explicit structural description of the half adder illustrated at Fig.1. Remember that this module only handles one bit of A and B. Problem 2: Complete module half_adder_im so that it is an implicit structural description of the
module half_adder_ex(s,c,a,b); input a, b; output s,c; // your solution goes here // endmodule //////////////////////////////////////////////////////////////////////////////// /// Problem 2 module half_adder_im(s,c,a,b); input a, b; output s,c; // your solution goes here endmodule //////////////////////////////////////////////////////////////////////////////// /// Problem 3 module full_adder(s,c,a,b,c1); input a, b,c1; output s,c; wire s_ha1, c_ha1, c_ha2; // your solution goes here endmodule /// Problem 4 module two_bit_adder(s,c,a,b,); input [1:0] a, b; output [1:0] s; output c; wire c_ha1;
// your solution goes here endmodule //////////////////////////////////////////////////////////////////////////////// /// Test Bench /// Do not modify test bench module test(); wire [2:0] sum1; reg [2:0] shadow_sum; reg [1:0] a, b; integer i; two_bit_adder adder1(sum1[1:0],sum1[2],a,b); task check_sum; input [2:0] s; input [79:0] name; if( s != shadow_sum ) begin $display("Wrong sum in %s: %d + %d = %d != %d\n", name, a, b, shadow_sum, s); $stop; end endtask initial begin for(i=0; i<=15; i=i+1) begin a = i[1:0]; b = i[3:2]; shadow_sum = a + b; #10; check_sum(sum1," twobit_adder");
