ECE 126 – VerilogA Tutorial: Creating Basic Analog Components: Inverter
Created at GWU by Thomas Farmer
Objectives:
•Create an inverter using verilogA
Assumptions:
•Student has successfully completed ECE 128 Lab 2 – Creating a resistor
Part I: Modeling a inverter in VerilogA:
1. Start the Cadence Virtuoso Framework
2. Select the ece128 Library from the Library Manager, create a new Cell:
File → New → Cellview
Name: inv
Type: VerilogA
3. Type the following code to model an inverter that uses a 5V power supply and has a
threshold voltage of 2.5V:
`include “constants.vams”
`include “disciplines.vams”
module inv (vout, vin);
electrical vout, vin;
parameter real vlogic_high = 5; // 5V Vdd
parameter real vlogic_low = 0; // 0V Vss
parameter real vtrans = 2.5; // threshold voltage
parameter real tdel=0.1n from [0:inf);// the bracket is not a typo
parameter real trise=0.1n from (0:inf);
parameter real tfall=0.1n from (0:inf);
real vout_val;
integer logic1;
analog begin
logic1 = V(vin) > vtrans;
@ (cross(V(vin) – vtrans, 1)) logic1 = 1;
@ (cross(V(vin) – vtrans, -1)) logic1 =0;
vout_val=(!logic1) ? vlogic_high: vlogic_low;
V(vout) <+ transition (vout_val, tdel, trise, tfall);
end
endmodule
4. Save and exit the editor, allow cadence to compile the verilogA code, correct any errors
5. Create a test bench cell called: inv_tb
◦Use a pulsed source (vpulse) and a 5ns transient simulation to test your inverter
◦View the output in spectre's waveform viewer and verify the inverter is working
properly
6. Read below to “understand” the verilogA code you've typed up above.
