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ECE 126 – NAND Gate Tutorial: Mixed Signal Simulation: Using Verilog as Input Stimulus
Created at GWU by Thomas Farmer
Objectives:
- Create a verilog test bench for a 2-input NAND gate
- Use verilog to verify output from a 2-input NAND gate
- Use the Cadence configuration hierarchy editor tool
Assumptions :
- Student has completed the Inverter Tutorial on Mixed Signal Simulation w/ Verilog
- Student has a basic familiarity with verilog
- Student is familiar with simulating off the ‘extracted view’ of a layout
Introduction :
Up to this point you have used “pulses” and “dc sources” in your test benches to test your Cadence schematics and layouts. In this lab you will learn to create and use a verilog ‘source’ to test your Cadence
schematics and layouts. This will enable you to create more complex test-benches for your final project.
LAB SETUP:
1. Ensure you have setup your environment as specified in the Inverter Tutorial on Mixed Signal
Simulation w/Verilog
2. Start Cadence
- In the Library Manager, look for a library called: analogLib
- If it IS present, skip to section labeled: “ Using Verilog to Test a 2-Input NAND Gate Layout ”
- If it is NOT present, proceed to step 3 below 3. Adding library: analogLib
- From the CIW window’s menu choose: Tools->Library Path Editor…
- When the Library Path Editor window opens, type the following line at the bottom of the list:
Library : analogLib Path : /apps/cadence/ic/tools/dfII/etc/cdslib/artist/analogLib
- From the menu choose: File->Exit. When prompted to save changes, answer yes.
- You will now see the analogLib library in the Library Manager window.
NOTE: Many screenshots are omitted from this tutorial, as it is assumed the student is now familiar with the
screens from the tutorial: ” Inverter Tutorial on Mixed Signal Simulation w/Verilog”
USING VERILOG TO TEST A 2-INPUT NAND GATE LAYOUT:
We will now repeat the process, but now for a two-input NAND gate. There are some differences between the work we’ve done in the last section and what must be done for a two-input NAND:
- The verilog code is slightly more complicated
- The wiring of the test-bench schematic is harder
- We will simulate off the extracted view of the NAND’s layout, as opposed to the schematic view.
- We will set the threshold voltage for a 1 and 0 (5V and 0V) in the simulator
- We will add additional verilog code to verify the NAND’s output, instead of simply generating the input
CREATING THE ANALOG-EXTRACTED VIEW:
1. Open the extracted view of the 2-input NAND created in HW # - Ensure the view was created with parasitic capacitances (if not, re-extract it) - Bring up the LVS form (Verify->LVS) - Run the LVS and ensure it passes (view the output log to make certain) - After successful LVS, click on “ Build Analog ” button - Click “ OK ” on the next form - Ensure there are no errors in the CIW window, then close the LVS and extracted view 2. Return the Library Manager - Ensure there is a NAND-2 “analog_extracted” view for the nand2 cell in the Library Manager - You may open the view if wish; it is identical in appearance to the extracted view - While this view appears identical to the extracted view, it is different at the netlist level. We will make use of this view later in the tutorial.
5. Ensure from the CIW, that there are 0 errors and 0 warnings in your verilog driver code.
CREATING THE MIXED SIGNAL TEST BENCH USING HEIRARCHY EDITOR:
**_1. Create a new “schematic” cell in the Digital Library, called: nand2_tb
- Arrange your schematic as follows, wire only as shown in this diagram:_**
- Instance the “ nand2_tb_vdriver ” that you made in the previous section of this tutorial
- Instance the “nand2” that you made in HW 1 (Digital->nand2)
- Wire up the output to a capacitor, and label the output ‘results’
- Leave space between the vdriver and the nand2 gate 3. Create a bus wire:
- Because the nand2_tb_vdriver has a 2-bit output, we need to create bus wire.
- From the schematic menu, choose: Create->Wire (wide)
- Create a short wire from the output of the vdriver, do NOT connect it directly to the NAND gate,
- End the wire by double clicking
- Now use a NARROW wire to connect from the bus to the “A” input of the NAND gate:
- Use a second NARROW wire to connect from the bus to “B” input, but make sure to create a
separate ‘solder dot’ as show here. Do not connect it to other narrow wire by mistake:
- You MUST now wire the bus and the individual wires for the simulator to separate the bus correctly. This step is not optional.
- From the menu choose: Create->Wire Name
Turn “ON” bus expansion
Ensure placement is “multiple”
**_4. In the Library Mangager, create a “config” view for the “nand2_tb2”
- The Hierarchy Editor will start:_**
- Use Template: SpectreVerilog
- Set cell to: nand2_tb
- Set view to: schematic
- Set Library List to: Digital analogLib NCSU_Analog_Parts
- Leave all other fields at default values, click OK 6. The Hierarchy Editor will appear
- In the cell bindings window, RIGHT click on the “View Found” for the nand2 cell
- Set the cell View-> analog_extracted
- From the main Hierarchy Editor Menu choose: View-> Update (Needed); click OK
- The list of components in the cell bindings list should be much longer after this step
- Now when you simulate your test-bench, it will simulate off the extracted view (essentially taking into account all the parasitics capacitances in your layout) o This will be extremely useful in your final project when calculating propagation delay.
- Choose File->Save & then close the Hierarchy Editor
RUNNING THE SIMULATION:
1. Once the Hierarchy Editor is closed, from the Library Manager, open the nand2_tb2->config view - Click “yes” to open both the config view & schematic view of the nand2_tb2 cell. **_2. Once the nand2_tb2 schematic opens, launch the ADE-L spectre simulator:
- From the menu, choose setup->Simulator/Directory/Host, set the Simulator to “spectreVerilog”
- Setup a 50us Transient Analysis, plot the outputs: results, test_data<1>, and test_data<0>
- Do NOT run the simulation! Keep the ADE-L window open in the background
- Return the nand2_tb2 schematic (it should be open)._**
- From its menu choose: Verimix->Interface Elements->Library
- Set the Model Parameters as follows:
- Change the Model IO to: output, set the model parameters as shown:
- Click OK when done
- Click Check and Save on the nand2_tb schematic window
- Return to the simulator window and run the simulation
VERIFYING THE OUTPUT OF THE NAND GATE USING VERILOG:
In your final project you may have many test cases. In this example, we only have 4 input combinations (00, 01, 10, 11). Say that you have 16 inputs and need to verify all the possible input/output combinations.
This can be done programmatically using verilog. In this part of the tutorial, you will create verilog code to verify the output waveforms, instead of just visually inspecting them as we have done up to now.
1. Keeping the simulator open, return to the schematic of the nand2_tb - Click on the “nand2_tb_vdriver” component. - Press the keys: X - Choose to “Descend” into the “ functional ” view of your vdriver, by clicking OK 2. GEDIT will open, now add the following lines of code to your verilog driver: - The highlighted lines indicate new code to add:
//Verilog HDL for "Digital", "nand2_tb_vdriver" "functional"
`timescale 10us/1us module nand2_tb_vdriver ( test_data, results );
input results ; output [1:0] test_data ; reg [1:0] test_data ;
initial begin $monitor ($time, " test_data=%b, results=%b", test_data, results);
test_data=2'b00;
#0.1 if (results == 1'b1) $display ("PASS: Inputs = %b, output = %b", test_data, results); else $display ("FAIL: Inputs = %b, output = %b", test_data, results);
#1 test_data=2'b01; #1 test_data=2'b10; #1 test_data=2'b11; #1 $finish ; end
endmodule
- Close GEDIT, saving your work, and ensure no compilation errors 3. Re-run the simulation from the ADE-L window:
- The graphs will show your inputs and outputs, verify that they are still correct
- The simulator will now have created 2 output windows. You may need to move one of them out of the way, they typically overlap each other
- Find the output from the simulator that looks like this:
- The output statements above are from your new verilog driver code
- Let’s review the verilog code and see how it produced this output:
$monitor ($time, " test_data=%b, results=%b", test_data, results);
- A $monitor statement in verilog spits out the values of the variables listed in it, every time the value of those variables change.
- By setting up a single $monitor statement, each time: test_data or the results variables change during simulation, we see their new value. That is how these outputs reached the screen: 0 test_data=00, results= 1 test_data=01, results= 2 test_data=10, results= 3 test_data=11, results= 3 test_data=11, results=
