Docsity
Docsity
Prepare for your exams
Prepare for your exams

Study with the several resources on Docsity

Earn points to download
Earn points to download

Earn points by helping other students or get them with a premium plan

Guidelines and tips
Guidelines and tips
Sell on Docsity
Sell on Docsity
Docsity AI
Docsity AI
Log inSign up

Prepare for your exams

Study with the several resources on Docsity

Find documents

Prepare for your exams with the study notes shared by other students like you on Docsity

Search for your university

Find the specific documents for your university's exams

Docsity AINEW

Summarize your documents, ask them questions, convert them into quizzes and concept maps

Explore questions

Clear up your doubts by reading the answers to questions asked by your fellow students

Earn points to download

Earn points by helping other students or get them with a premium plan

Share documents
download point icon20 Points

For each uploaded document

Answer questions
download point icon5 Points

For each given answer (max 1 per day)

All the ways to get free points
Get points immediately

Choose a premium plan with all the points you need

Study Opportunities

Choose your next study program

Get in touch with the best universities in the world. Search through thousands of universities and official partners

Community

Ask the community

Ask the community for help and clear up your study doubts

Free resources

Our save-the-student-ebooks!

Download our free guides on studying techniques, anxiety management strategies, and thesis advice from Docsity tutors

DRAM Controller Design: VHDL Coding for Read and Write Cycles - Prof. Janos L. Grantner, Lab Reports of Digital Systems Design

Western Michigan University (WMU)Digital Systems Design
Prof. Janos L. Grantner

The objectives and tasks for designing a dram controller using vhdl. Students are required to develop vhdl code for simple read and write cycles, implement delays using a finite state machine, and revise the vhdl programs to create a single dramc state machine. Detailed specifications and instructions for running simulations and verifying the correct operation of the circuit on a nexys 2 board.

Typology: Lab Reports

Pre 2010

Uploaded on 07/22/2009

koofers-user-5el
koofers-user-5el 🇺🇸

9 documents

1 / 2

Toggle sidebar

This page cannot be seen from the preview

Don't miss anything!

bg1
Laboratory Eight
Controller for DRAM chip
Objectives:
i. To develop VHDL code for synchronous sequential circuits
ii. To implement delays using a finite state machine
iii. To design a controller for simple read and write cycles of a DRAM chip
Task One
1. Devise VHDL code to control a simple read cycle for a DRAM chip. The read cycle timing
diagram and the AC Parameters of the DRAM chip are posted on the Class Web Page. The
detailed specifications are given in the Prelab Assignment, or will be decided by your Lab
TA. Your FSM will be using the 50MHz clock source on your Nexys 2 Board for the DRAM
Controller (DRAMC). Verify the correct operation of the 50MHz clock circuit with the help
of a logic analyzer. The read command signal that initiates the read cycle should be driven
by a function generator. The status of the key DRAM control signals should be checked by a
logic analyzer. The detailed specifications are given in the Prelab Assignment, or will be
decided by your Lab TA. Run behavioral and post-routing simulations to verify the correct
operation of your circuit.
2. Run the implement step and download the configuration bit file to your Nexys 2 Board. The
pin assignments for the input and output signals are specified in the Prelab Assignment, or
determined by your Lab TA. Use a function generator and a logic analyzer to verify the
correct operation.
Task Two
1. Devise VHDL code to control a simple write cycle for a DRAM chip. The write cycle timing
diagram and the AC Parameters of the DRAM chip are posted on the Class Web Page. The
detailed specifications are given in the Prelab Assignment, or will be decided by your Lab
TA. Again, your FSM will be using the 50MHz clock source on your Nexys 2 Board for the
DRAM Controller (DRAMC). The write command signal that initiates the read cycle should
be driven by a function generator. The status of the key DRAM control signals should be
checked by a logic analyzer. The detailed specifications are given in the Prelab Assignment,
or will be decided by your Lab TA. Run behavioral and post-routing simulations to verify
the correct operation of your circuit.
2. Run the implement step and download the configuration bit file to your Nexys 2 Board. The
pf2

Partial preview of the text

Download DRAM Controller Design: VHDL Coding for Read and Write Cycles - Prof. Janos L. Grantner and more Lab Reports Digital Systems Design in PDF only on Docsity!

Laboratory Eight

Controller for DRAM chip

Objectives:

i. To develop VHDL code for synchronous sequential circuits

ii. To implement delays using a finite state machine

iii. To design a controller for simple read and write cycles of a DRAM chip

Task One

  1. Devise VHDL code to control a simple read cycle for a DRAM chip. The read cycle timing diagram and the AC Parameters of the DRAM chip are posted on the Class Web Page. The detailed specifications are given in the Prelab Assignment, or will be decided by your Lab TA. Your FSM will be using the 50MHz clock source on your Nexys 2 Board for the DRAM Controller (DRAMC). Verify the correct operation of the 50MHz clock circuit with the help of a logic analyzer. The read command signal that initiates the read cycle should be driven by a function generator. The status of the key DRAM control signals should be checked by a logic analyzer. The detailed specifications are given in the Prelab Assignment, or will be decided by your Lab TA. Run behavioral and post-routing simulations to verify the correct operation of your circuit.
  2. Run the implement step and download the configuration bit file to your Nexys 2 Board. The pin assignments for the input and output signals are specified in the Prelab Assignment, or determined by your Lab TA. Use a function generator and a logic analyzer to verify the correct operation.

Task Two

  1. Devise VHDL code to control a simple write cycle for a DRAM chip. The write cycle timing diagram and the AC Parameters of the DRAM chip are posted on the Class Web Page. The detailed specifications are given in the Prelab Assignment, or will be decided by your Lab TA. Again, your FSM will be using the 50MHz clock source on your Nexys 2 Board for the DRAM Controller (DRAMC). The write command signal that initiates the read cycle should be driven by a function generator. The status of the key DRAM control signals should be checked by a logic analyzer. The detailed specifications are given in the Prelab Assignment, or will be decided by your Lab TA. Run behavioral and post-routing simulations to verify the correct operation of your circuit.
  2. Run the implement step and download the configuration bit file to your Nexys 2 Board. The

pin assignments for the input and output signals are specified in the Prelab Assignment, or determined by your Lab TA. Again, verify the correct operation.

Task Three

  1. Revise the VHDL programs you have developed for Tasks 1 and 2 such that you will create a single DRAMC state machine that is capable to run either a read or a write cycle for the DRAM chip. Run behavioral and post-routing simulations to verify the correct operation of your revised DRAMC circuit. 2. Run the implement step and download the configuration bit file to your Nexys 2 Board. The pin assignments for the input and output signals are specified in the Prelab Assignment, or determined by your Lab TA. Again, verify the correct operation for both the read and the write cycle.

Demonstrate these tasks to your Lab TA. All circuit designs and tests should be documented by VHDL source files, resource allocations and pin assignments from the Pad Reports, simulation timing diagrams and logic analyzer screen shots, as appropriate. You should also furnish your schematic diagram for Tasks One to Three. All VHDL files, simulation timing diagrams and logic analyzer screen shots should be commented on for full credit.