ECE 3550 DIGITAL DESIGN
Fall 2008
Prelab Assignment for Lab Nine
The microprocessor interface to the I/O chip is only enabled when the CS* (Chip
Select, active-low) signal is at low level. If CS* is at high level then the D7,…, D0
data bus signals must be in high-impedance state. Signals WR* (write) and RD*
(read) cannot be asserted simultaneously (they are mutually exclusive). Signal RDY*
should be asserted when CS* and either WR* or RD* are asserted.
The data on the D7,…, D0 lines should be captured in the POUT_reg register at the ↑
edge of the WR* signal while CS*=0 and A1=A0=0.
When generated, signal OUT* must have a pulse width of at least 60ns.
It is guaranteed that the minimum pulse with for signal INP* is at least 70ns. It is
also guaranteed that the data on the P7,…, P0 peripheral data lines is stable when
INP* is asserted. Signal INP* can be asserted at any point in time and the data on the
PIN7,…, P0 lines should be captured in the PIN_reg register regardless of the status
of the signals of the microprocessor interface.
Register bit INP_S* is cleared when the low level of signal INP* is sensed by the I/O
chip and it set back to high by the ↑ edge of the RD* signal while CS*=0 and
A1=A0=1.
When signal RESET* is asserted signal OUT* and register INP_S* should return to
high level.
The source of the I/O chip’s CLK signal is the 50MHz clock available on the Nexys
2 Board.
The programmer’s model (the microprocessor interface) is as follows:
CS* A1A0 WR* RD* D7… D0 POUT_reg7… 0 OUT* INP*
1 X X X X Z….Z no change 1 X
0 0 0 ↑ 1 data D7….D0 1 X
0 0 1 ↑ 1 X…X 1 no change -ve pulse X
0 1 0 1 0 PIN_reg7…0 no change 1 X
0 1 1 1 0 X…X INP_S* no change 1 X
