ECE 3550 DIGITAL DESIGN
FALL 2008
Homework Assignment #5
Total: 80 pts.
Due 11:30am, Friday, October 17, 2008
Asynchronous sequential circuit is given by its state transition graph on Page 2. Use the
Xilinx Project Navigator to design, functionally simulate and compile your circuit on
your Xilinx XC3S500E-FG320-5 chip. However, downloading the bit file to your Nexys
2 Board is NOT required.
Tasks:
a) Design the circuit using VHDL. Run the Implement Step to compile your design.
Give a hard copy of your .vhd file that was compiled without any errors. In
addition, turn in the pin assignment and the resource allocation segments of the
Pad Report. (40 pts.)
b) Develop a simulation script file (.do file) to verify the correct operation of your
circuit using ModelSim. The script must guarantee that every state and every state
transition, respectively, is visited at least once. Turn in a hard copy of your .do
file along with a print out of the post-routing simulation waveforms. Comment
on the results with respect to the original state transition graph for full credit.
(40
pts.)
Fall back position: turn in your .vhd and .do files for partial credit if you couldn’t
synthesize your design due to some fatal error.