ECE 3550 DIGITAL DESIGN
FALL 2008
Homework Assignment #8
Total: 90 pts.
Due 11:30am, Wednesday, November 12, 2008
An asynchronous sequential logic circuit is given on Page 2 by its primitive flow map
(i.e., initial state table) where X1 and X2 are inputs and Z is the circuit output.
a) Reduce the number of states using the method you have learned in class (Implication
Table, compatible states, Cover Table). In addition, check to see whether the closure
criteria is met by using a Closure Table. Try to make the classes of compatible states
disjoint. Give the reduced state table. (36 pts.)
b) Use the methods you have learned in class to a make critical-race free state
assignment. Show your assigned state table. (16 pts.)
c) Check for essential hazards. Give the path for each (if any). Eliminate them (if any)
and explain how it can be done. (20 pts.)
d) Assume the circuit will be implemented as combinational logic with feedback.
Minimize the next state equations and the output function using K-maps. Make sure
that all potential static hazards are eliminated. Give your Boolean functions in SOP
or in POS form, whichever is simpler. (18 pts.)