ECE 3550 DIGITAL DESIGN
FALL 2008
Homework Assignment #9
Total: 75 pts.
Due 11:30am, Friday, November 21, 2008
An asynchronous sequential logic circuit is given on Page 2 by its reduced state table
where X1 and X2 are inputs and Z is the circuit output. An active low RESET* signal
should be used to bring the circuit to state “a”.
Tasks:
a) Use the methods you have learned in class to a make critical-race free state
assignment. Show your assigned state table. All potential hang states should be
eliminated. Use the K-map template given on Page 2. (15 pts.)
b) Check for essential hazards. Give the path for each (if any). Eliminate them (if any)
and explain how it can be done. (15 pts.)
c) Assume the circuit will be implemented by using combinational logic with feedback.
Minimize the next state equations and the output function using K-maps. Make sure
that all potential static hazards are eliminated. Give your Boolean functions in SOP (or
POS) form. Use the K-map template given on Page 2. (15 pts.)
d) Design the circuit using VHDL. Run the Implement Step to compile your design to
the Spartan 3E FPGA chip on your Nexys 2 Board. Give a hard copy of your .vhd
file
that was compiled without any errors. In addition, turn in the pin assignment and the
summary of resource allocations segments of the Pad Report. (15 pts.)
e) Develop a simulation script file (.do file) to verify the correct operation of your
circuit using ModelSim. The script must guarantee that every state and every state
transition, respectively, is visited at least once. Make sure that you provide
enough time between input changes for the circuit to reach the next stable state.
Turn in a hard copy of your .do file along with a print out of the post-routing
simulation waveforms. Comment on the results with respect to the reduced state
table for full credit. (25 pts.)