Homework 2 - Digital Design - Fall 2008 | ECE 3550, Assignments of Digital Systems Design

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ECE 3550 DIGITAL DESIGN FALL 2008 Homework Assignment #2 Total: 50 pts. Due 11:30am, Wednesday, September 24, 2008 1. May static and/or dynamic hazards, respectively, possibly occur at the output of the combinational circuit given by the logic functions below? If your answer is a yes, for what input combinations may those hazards take place and how can they be eliminated’ For potential fixes, only logic functions should be given. Follow the procedure presented in class to solve this problem. Use the template given for your K-maps. Simple yes, o1 no answers will not be given credit. F =F, XOR F, where XOR stands for Exclusive OR F,=BC’+ AB’D+A’B’D where ‘ stands for Complement F,= A’C + BC’D’ + AB’C (30 pts.) 2. a) Give the simplest, static hazard-free POS implementation of the Boolean function F (A,B,C,D) = 1G, 7, 8, 9, 12, 13, 14) - d(0, 2, 3, 4, 5, 10) in algebraic form (A is most significant, d stands for “don’t care”). Use the template K- map given below. (12 pts.) b) Draw a circuit diagram for your solution using NOR gates only. Only non-inverted input signals are available. (8 pts.) A A.