EECS 312: Digital Integrated Circuits
Design Project
Teacher: Robert Dick
GSI: David Bild
Assigned: 5 April
Due: 21 April
1 Assignment
Design a CMOS eight-input synchronous falling-edge triggered parity gate that outputs a 1 if and only if an
odd number of its inputs are 1. Please keep the setup time small, i.e., make sure you have a latch or flip-flop
immediately at the input. Minimize the gate’s energy–period product, where energy is computed during one
clock period. Be sure to consider the gate’s energy–period product for a worst-case delay input transition
with the maximal number of input bit transitions. You should consider a few input transitions in order to
identify the worst case. Your test set should at least include the following transitions: 00000000→01111111,
01010101→10101011, and 00001111→11111000. Evaluate the performance when driving an inverter with
4×the minimal NMOSFET width, and twice that width for the PMOSFET. Measure the delay only to the
input of this inverter. The input transitions should have 100 ps rise and fall times.
Your VDD may be any value below 2.5V but you may only use one VDD for the entire design. You are free
to change transistor widths but please use default dopant concentrations and transistor lengths. You are
encouraged to use hierarchical design. You can find a reference on this at the course website.
2 Deliverables
70% of the grade will be based on functional correctness. 30% will b e based on design optimality. Please
turn in your complete schematics, as well as a transient analysis timing plot and a power plot illustrating
a worst-case delay transition with a maximal number of switching input bits. Please report your design’s
energy, period, and energy–period product. In addition to showing the plots and metrics for your design’s
worst-case input transition, also provide plots and metrics for the three example transitions given above.