Homework Four
EECS 312: Digital Integrated Circuits
Teacher: Robert Dick
Assigned 27 March
Due 2 April
You may discuss the assignment with your classmates. However, you need to understand and write the
solutions independently.
1. (10 pts.) In the latch in the following figure, compute the setup time when Dis low (that is, a low
value is being passed from Dto X). Assume the initial voltage at node Xis (VDD −VTn (Vx)) = 1.8 V.
You must compute the equivalent resistance of the pass transistor at the midpoint of the voltage swing
of interest. Let the width of the NMOS pass transistor be W=1 µm and the PMOS/NMOS sizes of
the inverter are 2µm and 1µm respectively. Use the 0.6 fF/µm junction capacitance assumption and
ignore overlap capacitance.
D
CLK
M1 Cx
Q
X
2. (15 total pts.) Assume the register shown below is driven at input Dby a CMOS inverter. A 4
cross-coupled inverters in the flip-flop have Wp=Wn= 0.5 µm and minimum channel length.
D
CLK CLK
X Y
Z
Q
(a) (7 pts.) Find a sizing constraint (or relationship between) on the inverter driving node D(not
shown explicitly in the diagram) and the NMOS pass transistor that ensures proper functionality
for storing a 0 (ignore body effect) at Q. You may need to make some simplifying assumptions
