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Material Type: Assignment; Professor: Dick; Class: Digit Integrat Circ; Subject: Electrical Engineering And Computer Science; University: University of Michigan - Ann Arbor; Term: Unknown 1989;
Typology: Assignments
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EECS 312: Digital Integrated Circuits
Teacher: Robert Dick Assigned 4 February Due 12 February
You may discuss the assignment with your classmates. However, you need to understand and write the solutions independently.
VSS VSS
Use Newton–Raphson iteration to compute the diode current.
VSS
VDD
Device B is a standard NMOSFET. Device A has the same properties as B, except that its device threshold voltage, VT is -0.4 V (it is negative). Assume that all the current equations and inequal- ity equations (to determine the mode of operation) for the depletion device A are the same as an enhancement-mode NMOSFET. VDD = 2.5 V.
(a) If V in = 0 V, what is V out? In steady state, what is the mode of operation for device A?
(b) Compute the output voltage for V in = 2.5 V. Solution Note: The region of operation for the FETs cannot be determined from simple ob- servation because the output voltage is determined by the fight between the two devices. In the following solution, multiple guesses for the operating region are made and then checked to determine which leads to a valid solution. However, notice that device appears to be an inverter (we saw a similar ratioed inverter, the resistive load inverter, in Lab 1). This aligns with our result from part A (a low input produces a high output) and suggests that for a high input, the output voltage should be close to Vss. Thus, it is reasonable to determine the operating modes if the output voltage is Vss, and then check that the resulting solution is consistent. That is, the computed value of Vout does not change the modes of operation.
(a) Considering only dynamic power consumption, calculate the power consumption of the IC and the amount of time before a fully charged battery is depleted.
(b) To obtain a more accurate estimate of battery life, now consider the added impact of subthreshold current. Calculate the static power consumption of the IC, assuming all nodes are driven by inverters. Recalculate the amount of time required to discharge a fully charged battery. By what percentage is the battery life reduced compared to (a)?
(c) Calculate the power consumption (static and dynamic) when the supply voltage is reduced to 1.3 V. You may assume that there is no timing slack at 1 GHz and that the frequency must, therefore, be reduced along with the voltage. You may use Figure 5–17 from the textbook to determine the resulting change in frequency, assuming that the delays of all combinational paths scale in proportion to the delay of an individual inverter. How long does a battery charge last with reduced voltage and frequency?
