Combinatorial Testing and Sequential Testing - Study Guide | EECS 312, Exams of Electrical and Electronics Engineering

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Testing Overview

Robert Dick

Combinational testing Sequential testing Fault modelsCombinational test generation

Outline

1. Combinational testing
2. Sequential testing

Combinational testing Sequential testing Fault modelsCombinational test generation

Introduction to testing

Determining the best way to test large circuits requires automation Building large circuits that are easy to test also requires automation Testing it spans all design, from system to physical level Today, I’ll introduce some classical ideas at the logic level

Combinational testing Sequential testing Fault modelsCombinational test generation

Section outline

1. Combinational testing Yield Fault models Combinational test generation

Combinational testing Sequential testing Fault modelsCombinational test generation

Defect level

Example acceptable defect level: ∼ 0. 0002 Either yield must be very high or fault coverage must be very high

d × 10 -

0.9 0.8 0.7 0.6^ 0. 1 y

99

100

c (%)

0

100

200

300

400

Combinational testing Sequential testing Fault modelsCombinational test generation

Section outline

1. Combinational testing Yield Fault models Combinational test generation

Combinational testing Sequential testing Fault modelsCombinational test generation

Functional testing

No assumptions about types of fault No assumptions about structure or properties of Circuit Under Test (CUT) The CUT is a black box that is checked to determine whether it responds to all (or most) input (sequences) as specified However, ignoring structural information makes testing unnecessarily slow

Combinational testing Sequential testing Fault modelsCombinational test generation

Structural testing

Use information about the specific CUT Types of faults that are likely to occur Structure of circuit

Combinational testing Sequential testing Fault modelsCombinational test generation

Fault models

bridging fault

z b

a

VDD

a z

b

VDD

VSS

Combinational testing Sequential testing Fault modelsCombinational test generation

Fault models

z b

a

VDD

a z

b

VDD

VSS

Combinational testing Sequential testing Fault modelsCombinational test generation

Fault models

z b

a

VDD

a z

b

VDD

VSS

Combinational testing Sequential testing Fault modelsCombinational test generation

Fault models

stuck−at fault

z b

a

VDD

a z

b

VDD

VSS

Combinational testing Sequential testing Fault modelsCombinational test generation

Singe stuck-at faults

One of the simplest and most common fault models S-a-0: Stuck-at 0 S-a-1: Stuck-at 1 Relies on digital reinforcement

1. 8 · VDD is 1 · VDD one logic stage later S-a-0.8 ≈ s-a- For two-level logic, exhaustive test set for single stuck-at faults will detect all multiple stuck-at faults, too Doesn’t hold for multi-level logic

Combinational testing Sequential testing Fault modelsCombinational test generation

Single stuck-at faults

Consider a NAND3 gate

Inputs fault z A B C free a b c z 0 1 0 1 0 1 0 1 0 0 0 1 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 0 1 0 1 1 1 1 0 1 1 1 1 0 1 1 0 0 1 1 1 1 1 1 1 0 1 1 0 1 1 1 1 1 0 1 1 0 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 0 1