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Solutions and common mistakes for midterm #1 of the eecs 145m spring 2001 course. It includes instructions for a digital i/o project, solutions for a license plate recognition system, and a 16-bit digital output port design. The document also includes warnings about common mistakes and misconceptions.
Typology: Exams
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1a
t d p d p
d p^ d^ m^ d^ p^ mp
σ (^) ∆ σ 2 σ 2 σ (^2) / σ^2 /
2a
remote μcomputer
camera and interface
input port
output port
central μcomputer input port
output port
data
data available
ready for data
2 b 1 car passes, remote computer acquires license plate number 2 remote computer stores license plate in local memory 3 remote computer waits until central computer signals “ready for data” TRUE (meanwhile steps 1 and 2 can continue and new license plate numbers can stack up in local memory) 4 remote computer writes license plate number to its output port and signals “data available” TRUE 5 central computer reads data, sets “ready for data” FALSE 6 remote computer sets “data available” FALSE
[4 points off for setting “data available” TRUE before the data have been asserted
A common mistake was to answer something like this: 1 car passes, remote computer acquires license plate number 2 remote computer stores license plate in local memory 3 remote computer signals “data available” TRUE (fundamental error here- “data available” should be set TRUE only after data are actually available to the receiver) 4 central computer detects “data available” TRUE and when ready sets “ready for data” TRUE 5 remote computer detects “ready for data” TRUE and asserts data on its input port 6 central computer reads data and sets “ready for data” FALSE 7 remote computer detects “ready for data” TRUE and sets “data available” FALSE
WHAT IS WRONG WITH THE ABOVE?
the central computer could perform steps 4 and 6 before step 5 is completed
Another common mistake was to think that the remote computer could “send” data to the central computer without any action on the part of the central computer. This appeared as the above with step 6 as 6 remote computer sends data to the central computer and sets “ready for data” FALSE
3a
μcomput
16-bit digital output port
(^12) D/A converter S/H
S/H
S/H
S/H
R1 R
L1 (^) L
A0 (^) R2 R
L2 L
R1, R3, L1, and L3 are digital control lines to S/H amps [2 points off for using only two S/H amps, a design that does not update both left and right within << 1 μs]
3 b 1 reset_clock; (this sets the clock to zero) 2 i= 3 write to output port, sending val_right[i] to the D/A, SAMPLE to R1 and HOLD to R3, L1, and L3 (during this 1 μs step the D/A output A0 can convert, glitch, and settle down; this stable analog voltage appears at R2) 4 write to output port, sending val_right[i] to the D/A, HOLD to R1, R3, L1, and L3 (this holds the new analog value on R2) 5 write to output port, sending val_left[i] to the D/A, SAMPLE to L1 and HOLD to L3, R1, and R3, (during this 1 μs step the D/A output A0 can convert, glitch, and settle down; this stable analog voltage appears at L2)
Midterm #1 class statistics:
Problem max average rms 1 20 18.0 2. 2 20 16.7 2. 3 60 47.4 9. total 100 82.1 10.
Grade distribution:
Range number approximate letter grade 61-65 1 C– 66-70 2 C 71-75 0 C+ 76-80 3 B 81-85 3 B+ 86-90 4 A– 91-95 0 A 96-100 2 A+