March 3, 2004 page 1 S. Derenzo
Solutions for Midterm #1 - EECS 145M Spring 2004
1a The edge-triggered D-type flip-flop has a digital input D, a clock input C, and a digital
output Q. On a rising edge of C, Q is set equal to D. Otherwise, Q is held constant.
1b The sample-and-hold amplifier has an analog input, a control input, and an analog output.
The control line selects sample mode (output = input) or hold mode (output held constant)
2This problem had two challenges (1) how to latch data changing every 10 ns and (2) how to
read 32 bits of those data using a 16-bit input port. Latching the data required using the DA
pulse (to know when the data were stable) and the comparator (so that the data were latched
only once per cycle of f(t)). Reading 32 bits of data with a 16 bit input port required tristate
buffers that were controlled by the computer. Latching had to be done in hardware in
nanoseconds, but reading was limited by the speed of the computer (microseconds).
Relevant Design Tip slides were # 6, 10, 11, 16, and 23.
Essential features for a successful solution:
•Comparator detects zero crossing
•DA from counter AND comparator used to latch data on flip-flops
•Counter data latched only once per comparator cycle (computer reads comparator and resets
S/R latch)
•Tri-state buffers used to read 32 bits from flip-flops into 16 bit input port
•Tri-state buffers enabled by computer output port
[4 points off for a design that merely counts comparator cycles in one second- this is not nearly
as accurate as timing the interval between comparator pulse edges with a 100 MHz clock]
2a
2b 1the program sets i = 1
2program resets the S/R latch
3program enables tri-state 5 to connect only the S/R latch to input bus*
16
Octal D-type
flip-flops 3,4
Octal D-type
flip-flops 1,2
16 Octal
tri-state
drivers 3,4
Octal
tri-state
drivers 1,2
octal
tri-state
driver
16 16
16
AND
Comparator
32-bit
100 MHz
counter
DA
16
Set
Reset
S/R
latch
C
C
Digital
output
port
Digital
input
port
Input
bus
V(t)
µComp
