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DOCUMENT NUMBER
9S12C128DGV1/D
©Motorola, Inc., 2002
MC9S12C Family
Device User Guide
V01.
Covers also
MC9S12GC Family
Original Release Date: 25 JAN 2003 Revised: 11 FEBRUARY 2004
Motorola, Inc.
Revision History
Version
Number
Revision
Date
Effective
Date Author^ Description of Changes
00.01 25.JAN.03 25.JAN.03 Original Version. Based on C32 user guide version 01. 00.02 07.FEB.03 07.FEB.03 Enhanced PortK descriptionPart number table revision in preface
00.03 25.FEB.03 25.FEB.
QFP112 Emulation pinout correction Enhanced part number explanation in preface Reduced pseudo STOP current spec. for C64,C96,C
00.04 15.APR.03 15.APR
Enhanced PortAD signal description Corrected VDDR description in 2.4. Revised pin leakage in electrical parameters
00.05 05.MAY.03 05.MAY.
SPI timing parameter table correction Output drive high value reduced in 3V range PE[4:2] Pull-Up spec out of reset changed 3V Expansion bus timing parameters not tested in production Minimum bus frequency specification increased to 0.25MHz. 00.06 21.MAY.03 21.MAY.03 Parameter classification added to Appendix Table C-2.IOH changed to 4mA for 3V range.
01.00 15.JUL.03 15.JUL
LVR level defined.for C32. Run IDD changed for C32. Block guide reference table updated Added PCB layout guide for Pierce oscillator configuration IOL parameter updated in 3.3V range 01.01 12.AUG.03 12.AUG.03 Updated PARTID listing due to C128 ECO revision
01.02 20.NOV.03 20.NOV.
Changed DOC number and CPU DOC reference number Included separate C32 LVI levels Changed PortM pull up reset state to enabled.
01.03 27.NOV.03 27.NOV.
Added References to the CAN-less GC-Family No major revision number increment, since silicon functionality is not changed. Added VDDX connection in PCB layout figures 8-1.to 8- Added Part ID for 2L45J mask set to Part ID table
01.04 27.JAN.04 27.JAN.
Table A-4 VDD/VDDPLL min when supplied externally now 2.35V Reference S12FTS128K1 in Preface (was S12FTS128K) Reference to CPU Guide corrected to Version
01.05 11.FEB.04 11.FEB.
Corrected flash sector sizes for C-Family devices with >64K Flash Corrected Preface Table 0-1 16K part listing to GC16 without CAN Added PPAGE specifications to memory map diagrams Added flash timing parameters for 1024 byte sector size
2.4.2 VDDR, VSSR — Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator
Section 3 System Clock Description
5.1 Overview.......................................................... 68
5.2 Vectors........................................................... 68
5.2.1 Vector Table..................................................... 68
5.3 Resets........................................................... 69
5.3.1 Reset Summary Table............................................. 70
5.3.2 Effects of Reset.................................................. 70
Section 6 HCS12 Core Block Description
6.1 Device-specific information............................................ 70
6.1.1 PPAGE......................................................... 70
6.1.2 BDM alternate clock............................................... 71
6.1.3 Extended Address Range Emulation Implications........................ 71
Section 7 Voltage Regulator (VREG) Block Description
7.1 Device-specific information............................................ 72
7.1.1 VREGEN....................................................... 72
7.1.2 VDD1, VDD2, VSS1, VSS2......................................... 72
Section 8 Recommended Printed Circuit Board Layout
Section 9 Clock Reset Generator (CRG) Block Description
9.1 Device-specific information............................................ 79
9.1.1 XCLKS........................................................ 80
Section 10 Oscillator (OSC) Block Description
Section 11 Timer (TIM) Block Description
Section 12 Analog to Digital Converter (ATD) Block Description
12.1 Device-specific information............................................ 80
12.1.1 VRL (voltage reference low)......................................... 80
Section 13 Serial Communications Interface (SCI) Block Description
Section 14 Serial Peripheral Interface (SPI) Block Description
Section 15 Flash Block Description
Figure D-3 48-pin LQFP Mechanical Dimensions (case no.932-03 ISSUE F)...... 130
Figure 19-1 Pin Assignments in 112-pin LQFP................................ 131
Figure 19-2 112-pin LQFP mechanical dimensions (case no. 987)80-pin QFP Mechanical Di- mensions (case no. 841B)
List of Tables
- 1.1 Overview. Section 1 Introduction
- 1.2 Features
- 1.3 Modes of Operation
- 1.4 Block Diagram
- 1.5 Device Memory Map.
- 1.6 Detailed Register Map
- 1.7 Part ID Assignments.
- 2.1 Device Pinout Section 2 Signal Description
- 2.2 Signal Properties Summary
- 2.2.1 Pin Initialization for 48 & 52 Pin LQFP bond-out versions
- 2.3 Detailed Signal Descriptions.
- 2.3.1 EXTAL, XTAL — Oscillator Pins
- 2.3.2 RESET — External Reset Pin
- 2.3.3 TEST / VPP — Test Pin
- 2.3.4 XFC — PLL Loop Filter Pin
- 2.3.5 BKGD / TAGHI / MODC — Background Debug, Tag High & Mode Pin
- 2.3.6 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins
- 2.3.7 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins
- 2.3.8 PE7 / NOACC / XCLKS — Port E I/O Pin
- 2.3.9 PE6 / MODB / IPIPE1 — Port E I/O Pin
- 2.3.10 PE5 / MODA / IPIPE0 — Port E I/O Pin
- 2.3.11 PE4 / ECLK— Port E I/O Pin [4] / E-Clock Output
- 2.3.12 PE3 / LSTRB — Port E I/O Pin [3] / Low-Byte Strobe (LSTRB).
- 2.3.13 PE2 / R/W — Port E I/O Pin [2] / Read/Write.
- 2.3.14 PE1 / IRQ — Port E input Pin [1] / Maskable Interrupt Pin
- 2.3.15 PE0 / XIRQ — Port E input Pin [0] / Non Maskable Interrupt Pin
- 2.3.16 PAD[7:0] / AN[7:0] — Port AD I/O Pins [7:0]
- 2.3.17 PP[7] / KWP[7] — Port P I/O Pin [7].
- 2.3.18 PP[6] / KWP[6]/ROMCTL — Port P I/O Pin [6]
- 2.3.19 PP[5:0] / KWP[5:0] / PW[5:0] — Port P I/O Pins [5:0]
- 2.3.20 PJ[7:6] / KWJ[7:6] — Port J I/O Pins [7:6]
- 2.3.21 PM5 / SCK — Port M I/O Pin
- 2.3.22 PM4 / MOSI — Port M I/O Pin
- 2.3.23 PM3 / SS — Port M I/O Pin 3.
- 2.3.24 PM2 / MISO — Port M I/O Pin
- 2.3.25 PM1 / TXCAN — Port M I/O Pin
- 2.3.26 PM0 / RXCAN — Port M I/O Pin
- 2.3.27 PS[3:2] — Port S I/O Pins [3:2]
- 2.3.28 PS1 / TXD — Port S I/O Pin
- 2.3.29 PS0 / RXD — Port S I/O Pin
- 2.3.30 PPT[7:5] / IOC[7:5] — Port T I/O Pins [7:5]
- 2.3.31 PT[4:0] / IOC[4:0] / PW[4:0]— Port T I/O Pins [4:0]
- 2.4 Power Supply Pins
- 2.4.1 VDDX,VSSX — Power & Ground Pins for I/O Drivers
- 2.4.3 VDD1, VDD2, VSS1, VSS2 — Internal Logic Power Pins
- 2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG
- 2.4.5 VRH, VRL — ATD Reference Voltage Input Pins
- 2.4.6 VDDPLL, VSSPLL — Power Supply Pins for PLL
- 4.1 Overview. Section 4 Modes of Operation
- 4.2 Chip Configuration Summary
- 4.3 Security.
- 4.3.1 Securing the Microcontroller
- 4.3.2 Operation of the Secured Microcontroller
- 4.3.3 Unsecuring the Microcontroller
- 4.4 Low Power Modes
- 4.4.1 Stop
- 4.4.2 Pseudo Stop.
- 4.4.3 Wait
- 4.4.4 Run.
- A.1 General. Appendix A Electrical Characteristics
- A.1.1 Parameter Classification
- A.1.2 Power Supply
- A.1.3 Pins
- A.1.4 Current Injection.
- A.1.5 Absolute Maximum Ratings
- A.1.6 ESD Protection and Latch-up Immunity
- A.1.7 Operating Conditions
- A.1.8 Power Dissipation and Thermal Characteristics
- A.1.9 I/O Characteristics
- A.1.10 Supply Currents
- B.1 Voltage Regulator Operating Conditions Appendix B Electrical Specifications
- B.2 Chip Power-up and LVI/LVR graphical explanation
- B.3 Output Loads
- B.3.1 Resistive Loads
- B.3.2 Capacitive Loads
- B.4 ATD Characteristics
- B.4.1 ATD Operating Characteristics In 5V Range
- B.4.2 ATD Operating Characteristics In 3.3V Range
- B.4.3 Factors influencing accuracy.
- B.4.4 ATD accuracy (5V Range)
- B.4.5 ATD accuracy (3.3V Range)
- B.5 NVM, Flash and EEPROM
- B.5.1 NVM timing.
- B.5.2 NVM Reliability.
- B.6 Reset, Oscillator and PLL.
- B.6.1 Startup
- B.6.2 Oscillator
- B.6.3 Phase Locked Loop
- B.7 MSCAN.
- B.8 SPI
- C.1 Master Mode. Appendix C Electrical Specifications
- C.2 Slave Mode.
- C.3 External Bus Timing
- C.3.1 General Muxed Bus Timing
- D.1 General. Appendix D Package Information
- D.2 80-pin QFP package.
- D.3 52-pin LQFP package.
- D.4 48-pin LQFP package.
- E.1 General. Appendix E Emulation Information
- E.1.1 PK[2:0] / XADDR[16:14].
- E.2 112-pin LQFP package.
- Figure 0-1 Order Part number Coding
- Figure 1-1 MC9S12C-Family Block Diagram
- Figure 1-2 MC9S12C128 and MC9S12GC128 User configurable Memory Map
- Figure 1-3 MC9S12C96 User Configurable Memory Map
- Figure 1-4 MC9S12C64 and MC9S12GC64 User Configurable Memory Map.
- Figure 1-5 MC9S12C32 and MC9S12GC32 User Configurable Memory Map.
- Figure 1-6 MC9S12GC16 User Configurable Memory Map
- Figure 2-1 Pin Assignments in 80 QFP for MC9S12C-Family
- Figure 2-2 Pin assignments in 52 LQFP for MC9S12C-Family.
- Figure 2-3 Pin Assignments in 48 LQFP for MC9S12C-Family
- Figure 2-4 PLL Loop Filter Connections
- Figure 2-5 Colpitts Oscillator Connections (PE7=1)
- Figure 2-6 Pierce Oscillator Connections (PE7=0)
- Figure 2-7 External Clock Connections (PE7=0)
- Figure 3-1 Clock Connections.
- Figure 8-1 Recommended PCB Layout (48 LQFP)
- Figure 8-2 Recommended PCB Layout (52 LQFP)
- Figure 8-3 Recommended PCB Layout (80 QFP)
- Figure 8-4 Recommended PCB Layout for 48 LQFP Pierce Oscillator
- Figure 8-5 Recommended PCB Layout for 52 LQFP Pierce Oscillator
- Figure 8-6 Recommended PCB Layout for 80QFP Pierce Oscillator
- Figure B-1 Voltage Regulator - Chip Power-up and Voltage Drops (not scaled)
- Figure B-2 ATD Accuracy Definitions
- Figure B-3 Basic PLL functional diagram
- Figure B-4 Jitter Definitions
- Figure B-5 Maximum bus clock jitter approximation
- Figure C-1 SPI Master Timing (CPHA=0)
- Figure C-2 SPI Master Timing (CPHA=1)
- Figure C-3 SPI Slave Timing (CPHA=0)
- Figure C-4 SPI Slave Timing (CPHA=1)
- Figure C-5 General External Bus Timing.
- Figure D-1 80-pin QFP Mechanical Dimensions (case no. 841B)
- Figure D-2 52-pin LQFP Mechanical Dimensions (case no. 848D-03)
- Table 0-2 MC9S12C-Family Package Option Summary
- Table 0-1 List of MC9S12C and MC9S12GC Family members.
- Table 0-3 MC9S12C-Family Part Number Coding.
- Table 0-4 MC9S12GC-Family Part Number Coding
- Table 0-5 Document References
- Table 1-1 Device Register Map Overview
- $0000 - $000FMEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface)
- $0010 - $0014 MMC map 1 of 4 (HCS12 Module Mapping Control)
- $0018 - $0018 Miscellaneous Peripherals (Device User Guide)
- $0019 - $0019 VREG3V3 (Voltage Regulator)
- $0015 - $0016 INT map 1 of 2 (HCS12 Interrupt)
- $0017 - $0017MMC map 2 of 4 (HCS12 Module Mapping Control)
- $001A - $001B Miscellaneous Peripherals (Device User Guide)
- $001C - $001D MMC map 3 of 4 (HCS12 Module Mapping Control,
- Device User Guide)
- $001E - $001E MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface)
- $001F - $001F INT map 2 of 2 (HCS12 Interrupt)
- $0020 - $002F DBG (including BKP) map 1 of 1 (HCS12 Debug)
- $0030 - $0031 MMC map 4 of 4 (HCS12 Module Mapping Control)
- $0032 - $0033 MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface)
- $0034 - $003F CRG (Clock and Reset Generator)
- $0040 - $006F TIM (Timer 16 Bit 8 Channels)
- $0070 - $007F Reserved
- $0080 - $009F ATD (Analog to Digital Converter 10 Bit 8 Channel)
- $00A0 - $00C7 Reserved
- $00D0 - $00D7 Reserved
- $00C8 - $00CF SCI (Asynchronous Serial Interface)
- $00D8 - $00DF SPI (Serial Peripheral Interface)
- $00E0 - $00FF PWM (Pulse Width Modulator)
- $0100 - $010F Flash Control Register
- $0110 - $013F Reserved
- $0140 - $017F CAN (Motorola Scalable CAN - MSCAN)
- Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout.
- $0180 - $023F Reserved
- $0240 - $027F PIM (Port Interface Module)
- $0280 - $03FF Reserved space
- Table 1-3 Assigned Part ID Numbers
- Table 1-4 Memory size registers
- Table 2-1 Signal Properties
- Table 2-2 MC9S12C-Family Power and Ground Connection Summary
- Table 4-1 Mode Selection
- Table 4-2 Clock Selection Based on PE7
- Table 5-1 Interrupt Vector Locations
- Table 5-2 Reset Summary
- Table 6-1 Device Specific Flash PAGE Mapping.
- Table 8-1 Recommended External Component Values.
- Table A-1 Absolute Maximum Ratings
- Table A-2 ESD and Latch-up Test Conditions
- Table A-3 ESD and Latch-Up Protection Characteristics
- Table A-4 Operating Conditions
- Table A-5 Thermal Package Characteristics
- Table A-6 5V I/O Characteristics
- Table A-7 3.3V I/O Characteristics
- Table A-8 Supply Current Characteristics for MC9S12C32
- Table A-9 Supply Current Characteristics for MC9S12C64,MC9S12C96,MC9S12C128
- Table B-1 Voltage Regulator Electrical Parameters
- Table B-2 Voltage Regulator - Capacitive Loads
- Table B-3 ATD Operating Characteristics
- Table B-4 ATD Operating Characteristics
- Table B-5 ATD Electrical Characteristics
- Table B-6 ATD Conversion Performance
- Table B-7 ATD Conversion Performance
- Table B-8 NVM Timing Characteristics
- Table B-9 NVM Reliability Characteristics.
- Table B-10 Startup Characteristics.
- Table B-11 Oscillator Characteristics
- Table B-12 PLL Characteristics
- Table B-13 MSCAN Wake-up Pulse Characteristics.
- Table C-1 Measurement Conditions
- Table C-2 SPI Master Mode Timing Characteristics.
- Table C-3 SPI Slave Mode Timing Characteristics.
- Table C-4 Expanded Bus Timing Characteristics (5V Range).
- Table C-5 Expanded Bus Timing Characteristics (3.3V Range)
Figure 0-1 Order Part number Coding
Table 0-3 MC9S12C-Family Part Number Coding
48LQFP MC9S12C64 MC9S12C64 TBD M, V, C
64K 4K
52LQFP MC9S12C64 MC9S12C64 TBD M, V, C 35
80QFP MC9S12C64 MC9S12C64 TBD M, V, C 60
48LQFP MC9S12C32 MC9S12C32 1L45J M, V, C
32K 2K
52LQFP MC9S12C32 MC9S12C32 1L45J M, V, C 35
80QFP MC9S12C32 MC9S12C32 1L45J M, V, C 60
48LQFP MC9S12GC128 MC9S12GC128 0L09S M, V, C
128K 4K
52LQFP MC9S12GC128 MC9S12GC128 0L09S M, V, C 35
80QFP MC9S12GC128 MC9S12GC128 0L09S M, V, C 60
48LQFP MC9S12GC128 MC9S12GC64 TBD M, V, C
64K 4K
52LQFP MC9S12GC128 MC9S12GC64 TBD M, V, C 35
80QFP MC9S12GC128 MC9S12GC64 TBD M, V, C 60
48LQFP MC9S12GC32 MC9S12GC32 1L45J M, V, C
32K 2K
52LQFP MC9S12GC32 MC9S12GC32 1L45J M, V, C 35
80QFP MC9S12GC32 MC9S12GC32 1L45J M, V, C 60
48LQFP MC9S12GC16 MC9S12GC16 1L45J M, V, C
16K 2K
52LQFP MC9S12GC16 MC9S12GC16 1L45J M, V, C 35
80QFP MC9S12GC16 MC9S12GC16 1L45J M, V, C 60
NOTES:
- Maskset dependent errata can be accessed at http://e-www.motorola.com/wbapp/sps/site/prod_summary.jsp
- C: TA = 85˚C, f = 25MHz. V: TA=105˚C, f = 25MHz. M: T (^) A= 125˚C, f = 25MHz
- All C-Family derivatives feature 1 CAN, 1 SCI, 1 SPI, an 8-channel A/D, a 6-channel PWM and an 8 channel timer. The GC-Family members do not have the CAN module
- I/O is the sum of ports capable to act as digital input or output.
Part Number Maskset Temp. Package Speed Description
MC9S12C128CFA16 TBD -40˚C, 85˚C 48LQFP 16MHz C128 die
Package Device Part Number Mask
1
set
Temp.^2
Options Flash^ RAM^ I/O^
MC9S12 C32 (P)C FU 25
Package Option Temperature Option
Device Title Controller Family
Temperature Options C = -40˚C to 85˚C V = -40˚C to 105˚C M = -40˚C to 125˚C Package Options FU = 80QFP PB = 52LQFP FA = 48LQFP
Speed Option
Speed Options 25 = 25MHz bus 16 = 16MHz bus
Preliminary Option
MC9S12C128CPB16 TBD -40˚C, 85˚C 52LQFP 16MHz C128 die MC9S12C128CFU16 TBD -40˚C, 85˚C 80QFP 16MHz C128 die MC9S12C128VFA16 TBD -40˚C,105˚C 48LQFP 16MHz C128 die MC9S12C128VPB16 TBD -40˚C,105˚C 52LQFP 16MHz C128 die MC9S12C128VFU16 TBD -40˚C, 105˚C 80QFP 16MHz C128 die MC9S12C128MFA16 TBD -40˚C,125˚C 48LQFP 16MHz C128 die MC9S12C128MPB16 TBD -40˚C,125˚C 52LQFP 16MHz C128 die MC9S12C128MFU16 TBD -40˚C, 125˚C 80QFP 16MHz C128 die MC9S12C128CFA25 TBD -40˚C, 85˚C 48LQFP 25MHz C128 die MC9S12C128CPB25 TBD -40˚C, 85˚C 52LQFP 25MHz C128 die MC9S12C128CFU25 TBD -40˚C, 85˚C 80QFP 25MHz C128 die MC9S12C128VFA25 TBD -40˚C,105˚C 48LQFP 25MHz C128 die MC9S12C128VPB25 TBD -40˚C,105˚C 52LQFP 25MHz C128 die MC9S12C128VFU25 TBD -40˚C, 105˚C 80QFP 25MHz C128 die MC9S12C128MFA25 TBD -40˚C,125˚C 48LQFP 25MHz C128 die MC9S12C128MPB25 TBD -40˚C,125˚C 52LQFP 25MHz C128 die MC9S12C128MFU25 TBD -40˚C, 125˚C 80QFP 25MHz C128 die MC9S12C96PCFA16 0L09S -40˚C, 85˚C 48LQFP 16MHz Preliminary C96 using C128 die MC9S12C96PCPB16 0L09S -40˚C, 85˚C 52LQFP 16MHz Preliminary C96 using C128 die MC9S12C96PCFU16 0L09S -40˚C, 85˚C 80QFP 16MHz Preliminary C96 using C128 die MC9S12C96CFA16 TBD -40˚C, 85˚C 48LQFP 16MHz Final C96 using C96 die MC9S12C96CPB16 TBD -40˚C, 85˚C 52LQFP 16MHz Final C96 using C96 die MC9S12C96CFU16 TBD -40˚C, 85˚C 80QFP 16MHz Final C96 using C96 die MC9S12C96PVFA16 0L09S -40˚C, 105˚C 48LQFP 16MHz Preliminary C96 using C128 die MC9S12C96PVPB16 0L09S -40˚C, 105˚C 52LQFP 16MHz Preliminary C96 using C128 die MC9S12C96PVFU16 0L09S -40˚C, 105˚C 80QFP 16MHz Preliminary C96 using C128 die MC9S12C96VFA16 TBD -40˚C,105˚C 48LQFP 16MHz Final C96 using C96 die MC9S12C96VPB16 TBD -40˚C,105˚C 52LQFP 16MHz Final C96 using C96die MC9S12C96VFU16 TBD -40˚C, 105˚C 80QFP 16MHz Final C96 using C96 die MC9S12C96PMFA16 0L09S -40˚C, 125˚C 48LQFP 16MHz Preliminary C96 using C128 die MC9S12C96PMPB16 0L09S -40˚C, 125˚C 52LQFP 16MHz Preliminary C96 using C128 die MC9S12C96PMFU16 0L09S -40˚C, 125˚C 80QFP 16MHz Preliminary C96 using C128 die MC9S12C96MFA16 TBD -40˚C,125˚C 48LQFP 16MHz Final C96 using C96 die MC9S12C96MPB16 TBD -40˚C,125˚C 52LQFP 16MHz Final C96 using C96 die MC9S12C96MFU16 TBD -40˚C, 125˚C 80QFP 16MHz Final C96 using C96 die MC9S12C96PCFA25 0L09S -40˚C, 85˚C 48LQFP 25MHz Preliminary C96 using C128 die MC9S12C96PCPB25 0L09S -40˚C, 85˚C 52LQFP 25MHz Preliminary C96 using C128 die MC9S12C96PCFU25 0L09S -40˚C, 85˚C 80QFP 25MHz Preliminary C96 using C128 die MC9S12C96CFA25 TBD -40˚C, 85˚C 48LQFP 25MHz Final C96 using C96 die MC9S12C96CPB25 TBD -40˚C, 85˚C 52LQFP 25MHz Final C96 using C96 die MC9S12C96CFU25 TBD -40˚C, 85˚C 80QFP 25MHz Final C96 using C96 die MC9S12C96PVFA25 0L09S -40˚C, 105˚C 48LQFP 25MHz Preliminary C96 using C128 die MC9S12C96PVPB25 0L09S -40˚C, 105˚C 52LQFP 25MHz Preliminary C96 using C128 die MC9S12C96PVFU25 0L09S -40˚C, 105˚C 80QFP 25MHz Preliminary C96 using C128 die
Part Number Maskset Temp. Package Speed Description
Table 0-4 MC9S12GC-Family Part Number Coding
MC9S12C64MFU25 TBD -40˚C, 125˚C 80QFP 25MHz Final C64 using C64 die MC9S12C32CFA16 1L45J -40˚C, 85˚C 48LQFP 16MHz C32 die MC9S12C32CPB16 1L45J -40˚C, 85˚C 52LQFP 16MHz C32 die MC9S12C32CFU16 1L45J -40˚C, 85˚C 80QFP 16MHz C32 die MC9S12C32VFA16 1L45J -40˚C,105˚C 48LQFP 16MHz C32 die MC9S12C32VPB16 1L45J -40˚C,105˚C 52LQFP 16MHz C32 die MC9S12C32VFU16 1L45J -40˚C, 105˚C 80QFP 16MHz C32 die MC9S12C32MFA16 1L45J -40˚C,125˚C 48LQFP 16MHz C32 die MC9S12C32MPB16 1L45J -40˚C,125˚C 52LQFP 16MHz C32 die MC9S12C32MFU16 1L45J -40˚C, 125˚C 80QFP 16MHz C32 die MC9S12C32CFA25 1L45J -40˚C, 85˚C 48LQFP 25MHz C32 die MC9S12C32CPB25 1L45J -40˚C, 85˚C 52LQFP 25MHz C32 die MC9S12C32CFU25 1L45J -40˚C, 85˚C 80QFP 25MHz C32 die MC9S12C32VFA25 1L45J -40˚C,105˚C 48LQFP 25MHz C32 die MC9S12C32VPB25 1L45J -40˚C,105˚C 52LQFP 25MHz C32 die MC9S12C32VFU25 1L45J -40˚C, 105˚C 80QFP 25MHz C32 die MC9S12C32MFA25 1L45J -40˚C,125˚C 48LQFP 25MHz C32 die MC9S12C32MPB25 1L45J -40˚C,125˚C 52LQFP 25MHz C32 die MC9S12C32MFU25 1L45J -40˚C, 125˚C 80QFP 25MHz C32 die
Part Number Maskset Temp. Package Speed Description
MC9S12GC128PCFA25 0L09S -40˚C, 85˚C 48LQFP 25MHz Preliminary GC128 using C128 die MC9S12GC128PCPB25 0L09S -40˚C, 85˚C 52LQFP 25MHz Preliminary GC128 using C128 die MC9S12GC128PCFU25 0L09S -40˚C, 85˚C 80QFP 25MHz Preliminary GC128 using C128 die MC9S12GC128CFA25 TBD -40˚C, 85˚C 48LQFP 25MHz Final GC128 using GC128 die MC9S12GC128CPB25 TBD -40˚C, 85˚C 52LQFP 25MHz Final GC128 using GC128 die MC9S12GC128CFU25 TBD -40˚C, 85˚C 80QFP 25MHz Final GC128 using GC128 die MC9S12GC128PVFA25 0L09S -40˚C, 105˚C 48LQFP 25MHz Preliminary GC128 using C128 die MC9S12GC128PVPB25 0L09S -40˚C, 105˚C 52LQFP 25MHz Preliminary GC128 using C128 die MC9S12GC128PVFU25 0L09S -40˚C, 105˚C 80QFP 25MHz Preliminary GC128 using C128 die MC9S12GC128VFA25 TBD -40˚C, 105˚C 48LQFP 25MHz Final GC128 using GC128 die MC9S12GC128VPB25 TBD -40˚C, 105˚C 52LQFP 25MHz Final GC128 using GC128 die MC9S12GC128VFU25 TBD -40˚C, 105˚C 80QFP 25MHz Final GC128 using GC128 die MC9S12GC128PMFA25 0L09S -40˚C, 125˚C 48LQFP 25MHz Preliminary GC128 using C128 die MC9S12GC128PMPB25 0L09S -40˚C, 125˚C 52LQFP 25MHz Preliminary GC128 using C128 die MC9S12GC128PMFU25 0L09S -40˚C, 125˚C 80QFP 25MHz Preliminary GC128 using C128 die MC9S12GC128MFA25 TBD -40˚C, 125˚C 48LQFP 25MHz Final GC128 using GC128 die MC9S12GC128MPB25 TBD -40˚C, 125˚C 52LQFP 25MHz Final GC128 using GC128 die MC9S12GC128MFU25 TBD -40˚C, 125˚C 80QFP 25MHz Final GC128 using GC128 die MC9S12GC64PCFA25 0L09S -40˚C, 85˚C 48LQFP 25MHz Preliminary GC64 using C128 die MC9S12GC64PCPB25 0L09S -40˚C, 85˚C 52LQFP 25MHz Preliminary GC64 using C128 die MC9S12GC64PCFU25 0L09S -40˚C, 85˚C 80QFP 25MHz Preliminary GC64 using C128 die
Part Number Maskset Temp. Package Speed Description
MC9S12GC64CFA25 TBD -40˚C, 85˚C 48LQFP 25MHz Final GC64 using GC64 die MC9S12GC64CPB25 TBD -40˚C, 85˚C 52LQFP 25MHz Final GC64 using GC64 die MC9S12GC64CFU25 TBD -40˚C, 85˚C 80QFP 25MHz Final GC64 using GC64 die MC9S12GC64PVFA25 0L09S -40˚C, 105˚C 48LQFP 25MHz Preliminary GC64 using C128 die MC9S12GC64PVPB25 0L09S -40˚C, 105˚C 52LQFP 25MHz Preliminary GC64 using C128 die MC9S12GC64PVFU25 0L09S -40˚C, 105˚C 80QFP 25MHz Preliminary GC64 using C128 die MC9S12GC64VFA25 TBD -40˚C, 105˚C 48LQFP 25MHz Final GC64 using GC64 die MC9S12GC64VPB25 TBD -40˚C, 105˚C 52LQFP 25MHz Final GC64 using GC64 die MC9S12GC64VFU25 TBD -40˚C, 105˚C 80QFP 25MHz Final GC64 using GC64 die MC9S12GC64PMFA25 0L09S -40˚C, 125˚C 48LQFP 25MHz Preliminary GC64 using C128 die MC9S12GC64PMPB25 0L09S -40˚C, 125˚C 52LQFP 25MHz Preliminary GC64 using C128 die MC9S12GC64PMFU25 0L09S -40˚C, 125˚C 80QFP 25MHz Preliminary GC64 using C128 die MC9S12GC64MFA25 TBD -40˚C, 125˚C 48LQFP 25MHz Final GC64 using GC64 die MC9S12GC64MPB25 TBD -40˚C, 125˚C 52LQFP 25MHz Final GC64 using GC64 die MC9S12GC64MFU25 TBD -40˚C, 125˚C 80QFP 25MHz Final GC64 using GC64 die MC9S12GC32PCFA25 1L45J -40˚C, 85˚C 48LQFP 25MHz Preliminary GC32 using C32 die MC9S12GC32PCPB25 1L45J -40˚C, 85˚C 52LQFP 25MHz Preliminary GC32 using C32 die MC9S12GC32PCFU25 1L45J -40˚C, 85˚C 80QFP 25MHz Preliminary GC32 using C32 die MC9S12GC32CFA25 TBD -40˚C, 85˚C 48LQFP 25MHz Final GC32 using GC32 die MC9S12GC32CPB25 TBD -40˚C, 85˚C 52LQFP 25MHz Final GC32 using GC32 die MC9S12GC32CFU25 TBD -40˚C, 85˚C 80QFP 25MHz Final GC32 using GC32 die MC9S12GC32PVFA25 1L45J -40˚C,105˚C 48LQFP 25MHz Preliminary GC32 using C32 die MC9S12GC32PVPB25 1L45J -40˚C,105˚C 52LQFP 25MHz Preliminary GC32 using C32 die MC9S12GC32PVFU25 1L45J -40˚C, 105˚C 80QFP 25MHz Preliminary GC32 using C32 die MC9S12GC32VFA25 TBD -40˚C,105˚C 48LQFP 25MHz Final GC32 using GC32 die MC9S12GC32VPB25 TBD -40˚C,105˚C 52LQFP 25MHz Final GC32 using GC32 die MC9S12GC32VFU25 TBD -40˚C, 105˚C 80QFP 25MHz Final GC32 using GC32 die MC9S12GC32PMFA25 1L45J -40˚C,125˚C 48LQFP 25MHz Preliminary GC32 using C32 die MC9S12GC32PMPB25 1L45J -40˚C,125˚C 52LQFP 25MHz Preliminary GC32 using C32 die MC9S12GC32PMFU25 1L45J -40˚C, 125˚C 80QFP 25MHz Preliminary GC32 using C32 die MC9S12GC32MFA25 TBD -40˚C,125˚C 48LQFP 25MHz Final GC32 using GC32 die MC9S12GC32MPB25 TBD -40˚C,125˚C 52LQFP 25MHz Final GC32 using GC32 die MC9S12GC32MFU25 TBD -40˚C, 125˚C 80QFP 25MHz Final GC32 using GC32 die MC9S12GC16PCFA25 1L45J -40˚C, 85˚C 48LQFP 25MHz Preliminary GC16 using C32 die MC9S12GC16PCPB25 1L45J -40˚C, 85˚C 52LQFP 25MHz Preliminary GC16 using C32 die MC9S12GC16PCFU25 1L45J -40˚C, 85˚C 80QFP 25MHz Preliminary GC16 using C32 die MC9S12GC16CFA25 TBD -40˚C, 85˚C 48LQFP 25MHz Final GC16 using GC16 die MC9S12GC16CPB25 TBD -40˚C, 85˚C 52LQFP 25MHz Final GC16 using GC16 die MC9S12GC16CFU25 TBD -40˚C, 85˚C 80QFP 25MHz Final GC16 using GC16 die MC9S12GC16PVFA25 1L45J -40˚C,105˚C 48LQFP 25MHz Preliminary GC16 using C32 die MC9S12GC16PVPB25 1L45J -40˚C,105˚C 52LQFP 25MHz Preliminary GC16 using C32 die MC9S12GC16PVFU25 1L45J -40˚C, 105˚C 80QFP 25MHz Preliminary GC16 using C32 die MC9S12GC16VFA25 TBD -40˚C,105˚C 48LQFP 25MHz Final GC16 using GC16 die MC9S12GC16VPB25 TBD -40˚C,105˚C 52LQFP 25MHz Final GC16 using GC16 die
Part Number Maskset Temp. Package Speed Description
