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Embedded Systems: Microcomputer-Based Systems and MC68HC11, Study notes of Electrical and Electronics Engineering

University of Utah (The U)Electrical and Electronics Engineering

An introduction to embedded computer systems, focusing on microcomputer-based systems and the motorola mc68hc11 microcontroller. Topics include the function of microcomputers, examples of embedded and general-purpose systems, real-time interfacing, and choosing a microcomputer. The document also covers the architecture, registers, and addressing modes of the mc68hc11, as well as assembly language instructions.

Typology: Study notes

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Uploaded on 08/30/2009

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Slide 1

ECE/CE 3720: Embedded System Design

(ECE 6960/2 and CS 6968)

Chris J. Myers

Lecture 1: Microcomputer-Based Systems

Slide 2

Embedded Computer Systems

•An embedded computer system is a system that includes a

microcomputer configured to perform a dedicated application.

•Software is typically fixed into ROM and not user accessible.

•Microcomputer is embedded, or hidden, inside the device.

•Typical automobile contains an average of 10 microcomputers.

•Upscale homes may have as many as 150 microcomputers.

•Average consumer interacts with µ-controllers 300 times/day.

Slide 3

Examples of Embedded Computer Systems

Slide 4

Examples of General-Purpose Computer Systems

Discover Study notes of Electrical and Electronics Engineering University of Utah (The U)

Partial preview of the text

Download Embedded Systems: Microcomputer-Based Systems and MC68HC11 and more Study notes Electrical and Electronics Engineering in PDF only on Docsity!

& Slide 1 '

&^ Slide 2 ' Lecture 1: Microcomputer-Based Systems Chris J. Myers(ECE 6960/2 and CS 6968) ECE/CE 3720: Embedded System Design

1 •^ Average consumer interacts with μ-controllers 300 times/day.^ •^ Upscale homes may have as many as 150 microcomputers.^ •^ Typical automobile contains an average of 10 microcomputers.^ •^ Microcomputer is embedded, or hidden, inside the device.^ •^ Software is typically fixed into ROM and not user accessible.microcomputer configured to perform a dedicated application.^ •^ An^ embedded computer system is a system that includes a^ Embedded Computer Systems

&^ Slide 3 '

&^ Slide 4 ' Examples of Embedded Computer Systems

2 Examples of General-Purpose Computer Systems

& Slide 5 ' % $

&^ Slide 6 ' in both digital and analog form. • Must learn how to interface many types of inputs and outputscomputer to communicate with the external hardware. • An interface is the hardware and software that allow the • Must learn features built into microcomputers to handle time.to perform the input/calculation/output sequence. • Real-time systems have an upper bound on the time requiredgenerate outputs. • Microcomputers accepts inputs, perform calculations, and Real-Time Interfacing

3 measurement^ –^ Output capture used for generating signals and frequency^ –^ Input capture used for period and pulse width measurement^ –^ Event counter system for advanced timer operations^ –^ Pulse-width-modulations (PWM) outputs^ –^ Pulse accumulator for external event counting^ –^ Computer Operating Properly (COP) protection^ –^ Fixed period rate interrupts^ –^ Analog-to-digital (ADC) converters^ –^ Asynchronous Serial Communication Interface (SCI)^ –^ Synchronous Serial Peripheral Interface (SPI)^ •^ Microcontrollers support many I/O features:^ Chip Peripherals and Timer Features

&^ Slide 7 '

&^ Slide 8 ' Microchip PIC12, PIC16, PIC17Siemens C500, C166, TricoreMitsubishi 740, 7600, 7700, M16CNEC 78KHitachi H8Philips 8051 Intel 8051, 80251, 8096, 8029668K, MCORE, Coldfire, PowerPC Motorola 68HC05, 68HC08, 68HC11, 68HC12, 68HC16, Company Products Microcomputer Architectures

4 –^ Power requirements.^ –^ Availability of compilers, simulators, and emulators.^ –^ Second source availability.^ –^ Package size and environmental issues.^ –^ Timer, PWM, and ADC requirements.^ –^ Number of parallel and serial ports needed.^ –^ Numerical or other special operations required.^ –^ 8-,16-, or 32-bit data size.^ –^ Speed and I/O bandwidth requirements for application.^ –^ ROM, RAM, and EEPROM size.^ –^ Labor, material, manufacturing, maintenance costs.^ •^ Many factors to consider when selecting a microcomputer:^ Choosing a Microcomputer

& Slide 13 ' % $

&^ Slide 14 ' B600 to B7FF 512 EEPROM Program and constants1000 to 103F 64 I/O 0000 to 01FF 512 RAM Variables and stack Address (hex) Size Device Contents Address Map for MC68HC11E1CP

7 MC68HC11 Registers

&^ Slide 15 '

$86 $64 ldaa 100 RegA = [100]Object code Instruction Comment^ •^ Assembly instructions are translated into machine code: here ldaa 100 RegA = [100]Label Opcode Operand(s) Comment^ •^ Assembly language instructions have four fields: Assembly Language

&^ Slide 16 '

8 •^ PC relative addressing mode (REL)^ •^ Indexed addressing mode (IND)^ •^ Extended addressing mode (EXT)^ •^ Direct page addressing mode (DIR)^ •^ Immediate addressing mode (IMM)^ •^ Inherent addressing mode (INH)^ MC68HC11 Addressing Modes

& Slide 17 ' % $

&^ Slide 18 ' $1B aba RegA = RegA + RegBObj code Op Comment • Has no operand field. Inherent Addressing Mode

9 $8E00FF^ lds^ #$00FF^ Initialize stackObj code^ Op^ Operand^ Comment^ •^ Data is included in the machine code.^ •^ Uses a fixed constant.^ Immediate Addressing Mode

&^ Slide 19 '

&^ Slide 20 ' $9632 ldaa 50 RegA = [$0032]Obj code Op Operand Comment • Uses an 8-bit address to access from addresses 0 to $00FF. Direct Page Addressing Mode

10 $FE8000^ ldx^ $8000^ RegX = [$8000]^ Obj code^ Op^ Operand Comment^ $B71004^ staa^ $1004^ [$1004] = RegAObj code^ Op^ Operand Comment^ •^ Usss a 16-bit address to access all memory and I/O devices.^ Extended Addressing Mode

& Slide 25 ' % $

(^) psha, (^) pshb, (^) pshx, (^) pshy, (^) pula, (^) pulb, (^) pulxoff of the stack.^ •^ Push and pull instructions used to put data onto and take data Other Data Movement Instructions , (^) puly (^) (all INH).
(^) tab, (^) tap, (^) tba, (^) tpa, (^) tsx, (^) tsy, (^) txs^ •^ Transfer instructions used to copy data between registers. , (^) tys (^) (all INH).

&^ Slide 26 ' – xgdx, xgdy (all INH).accumulator D and index registers X and Y. • Exchange instructions used to exchange data between

13 $1838^ puly^ INH$38^ pulx^ INH$33^ pulb^ INH$32^ pula^ INH$06^ tap^ INH^ $32^ pula^ INH body of subroutine$36^ psha^ INH$07^ tpa^ INH$36^ psha^ INH$37^ pshb^ INH$3C^ pshx^ INH^ $183C^ pshy^ INH^ Obj code^ Op^ Operand Comment^ Example: Saving State to Stack

&^ Slide 27 '

(^) Used to initialize memory (clr), accumulators (clra Clear/Set Instructions ,clrb), or

&^ Slide 28 ' CCR can also be set (sec, (^) sei, (^) sev). • (^) The carry (C), interrupt mask (I), and overflow (V) bits in the$7F0025 (^) clr (^) $0025 (^) EXT$9725 (^) staa (^) $25 (^) DIR $4F (^) clra (^) INHObj code (^) Op (^) Operand (^) Comment • (^) Examples: • (^) clra, (^) clrb, (^) clc, (^) cli, (^) clv (^) are INH. • (^) clr (^) addressing modes are: EXT, IND.bits in the CCR (clc, (^) cli, (^) clv).

(^) With carry to memory: (^) adca, (^) adcb, (^) sbca, (^) sbcb • (^) Registers: (^) aba, (^) abx, (^) aby, (^) sba (^) (all INH). Add and Subtract Instructions .
(^) w/o carry to memory: (^) adda, (^) addb , (^) addd, (^) suba, (^) subb, (^) subd. 14 $9744^ staa^ $44^ store most sig byte$9934^ adca^ $34^ add data at $34 to A$9624^ ldaa^ $24^ load most sig byte$9745^ staa^ $45^ store least sig byte$9B35^ adda^ $35^ add data at $35 to A^ $9625^ ldaa^ $25^ load least sig byteObj code^ Op^ Operand (^) Comment^ •^ Examples: 16-bit addition using only A^ •^ Addressing modes are: IMM, DIR, EXT, IND.

& Slide 29 ' % $

16-bit unsigned product stored in D (i.e., A × B → D^ •^ Multiplies two unsigned 8-bit values in A and B to produce a Multiply Instruction

&^ Slide 30 ' • (^) At the end, accumulator (^) D (^) contains $13EC. $3D (^) mul (^) INH $C614 (^) ldab (^) #$14 (^) IMM $86FF (^) ldaa (^) #$FF (^) IMMObj code (^) Op (^) Operand (^) Comment • (^) Example: % $

fraction between 0 and 0.999998 (i.e., (65536 ∗ D)/X •^ fdiv performs fractional division resulting in binary weighted^ •^ idiv performs integer division.^ •^ Resultant placed in X register and remainder in D register.^ •^ Use D register for the dividend and X register for the divisor. Divide Instructions

→ X).

$CCFFFF (^) ldd (^) #$FFFF (^) After (^) idiv Obj code (^) Op (^) Operand (^) Comment^ •^ Example: (^) executes $CC0003 (^) ldd (^) #$03 (^) After (^) fdiv $02 (^) idiv (^) D contains $159F $CE2710 (^) ldx (^) #$2710 (^) X contains $ (^) executes 15 $03^ fdiv^ D contains $0000^ $CE0006^ ldx^ #$06^ X contains $

&^ Slide 31 '

&^ Slide 32 ' • If Z flag is 1 then the contents of $1031 equals $50.$B11031 cmpa $1031 compare A to memory $8650 ldaa #$50 load set point into AObj code Op Operand Comment • Example: comparing with a known set point • Addressing modes: IMM, DIR, EXT, IND • Compare to memory: cmpa, cmpb, cpd, cpx, cpy. • Compare registers: cba (INH). • Typically used just before a branch instruction.any data. • Perform a subtraction to update the CCR, but do not alter Compare Instructions

(^) tst, (^) tsta, (^) tstb (^) - test for zero or minus and set • (^) neg, (^) nega, (^) negb (^) - two’s complement. • (^) inc, (^) inca, (^) incb, (^) ins, (^) inx, (^) iny (^) - increment • (^) dec, (^) deca, (^) decb, (^) des, (^) dex, (^) dey (^) - decrement • (^) daa (^) - decimal adjust A for BCD. Miscellaneous Arithmetic Instructions (^) Z (^) and (^) N (^) flags 16 in the CCR.

& Slide 37 ' % $

&^ Slide 38 ' • brn - branch never • bvs - branch if overflow set (i.e., V = 1). • bvc - branch if overflow clear (i.e., V = 0). • bmi - branch if negative (i.e., N = 1). • bpl - branch if positive or zero (i.e., N = 0). • beq - branch if equal to zero (i.e., Z = 1). • bne - branch if not equal to zero (i.e., Z = 0). • bcs - branch if carry set (i.e., C = 1). • bcc - branch if carry clear (i.e., C = 0). Single Condition Branches

(^) These branches usually follow (^) cba, (^) cmp(A,B,D), Unsigned Number Branches (^) cp(X,Y), (^) sba,
(^) bhi (^) - branch if higher ’>’ (i.e., (^) C (^) + sub(A,B,D) (^) instructions. Z (^) = 0).
(^) bhs (^) - branch if higher or same ’≥’ (i.e., (^) C (^) = 0).
(^) bls (^) - branch if lower or same ’≤’ (i.e., • (^) blo (^) - branch if lower ’<’ (i.e., (^) C (^) = 1). (^19) C (^) + (^) Z (^) = 1).

&^ Slide 39 '

(^) These branches usually follow (^) cba, (^) cmp(A,B,D), (^) cp(X,Y) Signed Number Branches , (^) sba,
(^) bgt (^) - branch if greater ’>’ (i.e., (^) Z (^) · (^) ( sub(A,B,D) (^) instructions. N (^) ⊕ (^) V (^) ) = 0).
(^) bge (^) - branch if greater or equal ’≥ ’ (i.e., (^) N (^) ⊕ (^) V (^) = 0).
(^) blt (^) - branch if less ’<’ (i.e., (^) N (^) ⊕ (^) V (^) = 1).
(^) ble (^) - branch if less or equal ’≤’ (i.e., (^) Z (^) · (^) (N (^) ⊕ (^) V (^) ) = 1).

&^ Slide 40 '

20 bit 4 of loc 5 is 0$13051005^ brclr^ 5,$10,$F889 goto $F889 ifbit 4 of loc 5 is 1^ $12051005^ brset^ 5,$10,$F889 goto $F889 ifObj code^ Op^ Operand^ Commentprovided and branches only when all bits in the mask are clear.^ •^ brclr^ - performs logical AND of memory address and maskprovided and branches only when all bits in the mask are set.^ •^ brset^ - performs logical AND of memory address and mask^ Bit Masking Branches

& Slide 41 ' % $

&^ Slide 42 ' • DelayT ime = t(ldab) + (t(decb) + t(bne)) × count bne Delay If B 6 = 0 goto Delay Delay decb decrement B ldab #$Count Load B with countLabel Op Operand Comment • Branch loops can be used to insert a time delay:C3F2 jmp PI PI may be any valid address.... C3B2 Next instructionC3B0 bcs $40Address Op Operand Comment • Use branch and jump to branch outside of range: Long Branches and Delays

21 stack and jumps to that location.^ •^ rts^ - return from subroutine, PC automatically pulled off thestack (least significant byte first).^ •^ On either^ bsr^ or^ jsr, PC is automatically pushed onto the^ •^ jsr^ - jumps to subroutine using DIR, EXT, or IND addressing.^ •^ bsr^ - branch to subroutine using REL addressing.^ Subroutine Calls and Return

&^ Slide 43 '

routine to restore the CPU registers.^ •^ rti instruction is called at the end of an interrupt service^ •^ swi instruction executes a software interrupt.external interrupt.^ •^ wai instruction puts CPU into standby mode waiting for an Interrupt Handling

&^ Slide 44 '

SP − 1 RETURN ADDRESS (P CH SP − 2 INDEX REGISTER (YL) H SP − 3 INDEX REGISTER (Y) L SP − 4 INDEX REGISTER (X) H SP − 5 INDEX REGISTER (X) SP − 6 ACCUMULATOR A SP − 7 ACCUMULATOR B SP − 8 CONDITION CODE SP − 9 STACK^ Storing the State on the Stack