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Material Type: Exam; Class: Embedded Microcomputer Systems; Subject: (Electrical and Comp Engr); University: University of Houston; Term: Unknown 2003;
Typology: Exams
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MOTOROLA.COM/SEMICONDUCTORS
S12CPUV2/D Rev. 0
S12CPUV
7/
Reference Manual S12CPUV 4 Revision History MOTOROLA
Revision History
Date RevisionLevel Description (^) Number(s)Page July, 2003 0 Initial release^ N/A
8 Table of Contents MOTOROLA
10 Table of Contents MOTOROLA
Table of Contents
Table of Contents
14 Table of Contents MOTOROLA
Reference Manual S12CPUV 16 List of Figures MOTOROLA
Table Title Page
S12CPUV2 Reference Manual
MOTOROLA Introduction 19
This manual describes the features and operation of the core (central processing unit, or CPU, and development support functions) used in all HCS12 microcontrollers. For reference, information is provided for the M68HC12.
The CPU12 is a high-speed, 16-bit processing unit that has a programming model identical to that of the industry standard M68HC central processor unit (CPU). The CPU12 instruction set is a proper superset of the M68HC11 instruction set, and M68HC11 source code is accepted by CPU12 assemblers with no changes.
20 Introduction MOTOROLA
The symbols and notation shown here are used throughout the manual. More specialized notation that applies only to the instruction glossary or instruction set summary are described at the beginning of those sections.
1.3.1 Abbreviations for System Resources
A — Accumulator A B — Accumulator B D — Double accumulator D (A : B) X — Index register X Y — Index register Y SP — Stack pointer PC — Program counter CCR — Condition code register S — STOP instruction control bit X — Non-maskable interrupt control bit H — Half-carry status bit I — Maskable interrupt control bit N — Negative status bit Z — Zero status bit V — Two’s complement overflow status bit C — Carry/Borrow status bit