Download Introduction to Microcomputer Embedded Systems - Final Exam | ECE 4437 and more Exams Electrical and Electronics Engineering in PDF only on Docsity!
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
DOCUMENT NUMBER
S12C32PIMV1/D
©Motorola, Inc., 2001
PIM_9C
Block Guide
V01.
Original Release Date: 20 AUG 2001 Revised: 04 Feb 2003
Motorola, Inc.
Revision History
Version
Number
Revision
Date
Effective
Date Author^ Description of Changes
V01.
20 AUG
20 AUG
Initial release of module specification in SRSv3 document format. Derived from module spec pim_9dp256.
V01.01 09 OCT
09 OCT
TPM replaced with PWM module, Timer extended => 16b8c, Module Routing Register MODRR added, reset values in PERS changed from %0011 to %
V01.02 12 OCT
12 OCT
- Section 1.1: Second sentence removed (related to design information)
- Block Diagram updated (PW -> PWM, routing of PWM 5 removed)
- Port T register naming changed (I/OCx -> IOCx)
- Section "48 & 52 pin bond-out version" removed
V01.
15 FEB
15 FEB
Section 3.3.1: Fuctional description changed, Table 3-3 added, Port AD: PERAD, PPSAD,RDRAD added
V01.
26 JUL
26 JUL
2002 Figure 3-39: PTIJ7, PTIJ6 replaced by PTIAD7, PTIAD
V01.
17 OCT
17 OCT
2002 Added document number, syntax clean-up
V01.
04 FEB
04 FEB
2003 Changed end sheet, removed note on page 35
- 1.1 Overview. Section 1 Introduction
- 1.2 Features
- 2.1 Overview. Section 2 External Signal Description
- 2.2 Signal properties.
- 3.1 Overview. Section 3 Memory Map/Register Definition
- 3.2 Module Memory Map
- 3.3 Register Descriptions
- 3.3.1 Port T Registers
- 3.3.2 Port S Registers
- 3.3.3 Port M Registers
- 3.3.4 Port P Registers
- 3.3.5 Port J Registers
- 3.3.6 Port AD Registers
- 4.1 General. Section 4 Functional Description
- 4.1.1 I/O register
- 4.1.2 Input register
- 4.1.3 Data direction register
- 4.1.4 Reduced drive register
- 4.1.5 Pull device enable register
- 4.1.6 Polarity select register
- 4.2 Port T
- 4.3 Port S
- 4.4 Port M
- 4.5 Port P
- 4.6 Port J
- 4.7 Port A, B, E and BKGD pin.
- 4.8 External Pin Descriptions
- 4.9 Low Power Options
- 4.9.1 Run Mode.
- 4.9.2 Wait Mode
- 4.9.3 Stop Mode
- 5.1 General. Section 5 Initialization/Application Information
- 5.2 Reset Initialization
- 6.1 General. Section 6 Interrupts
- 6.2 Interrupt Sources
- 6.3 Recovery from STOP
- Figure 1-1 PIM_9C32 Block Diagram List of Figures
- Figure 3-1 Port T I/O Register (PTT).
- Figure 3-2 Port T Input Register (PTIT)
- Figure 3-3 Port T Data Direction Register (DDRT)
- Figure 3-4 Port T Reduced Drive Register (RDRT)
- Figure 3-5 Port T Pull Device Enable Register (PERT)
- Figure 3-6 Port T Polarity Select Register (PPST)
- Figure 3-7 Port T Module Routing Register (MODRR)
- Figure 3-8 Port S I/O Register (PTS)
- Figure 3-9 Port S Input Register (PTIS)
- Figure 3-10 Port S Data Direction Register (DDRS)
- Figure 3-11 Port S Reduced Drive Register (RDRS)
- Figure 3-12 Port S Pull Device Enable Register (PERS)
- Figure 3-13 Port S Polarity Select Register (PPSS)
- Figure 3-14 Port S Wired-Or Mode Register (WOMS)
- Figure 3-15 Port M I/O Register (PTM)
- Figure 3-16 Port M Input Register (PTIM).
- Figure 3-17 Port M Data Direction Register (DDRM)
- Figure 3-18 Port M Reduced Drive Register (RDRM).
- Figure 3-19 Port M Pull Device Enable Register (PERM).
- Figure 3-20 Port M Polarity Select Register (PPSM)
- Figure 3-21 Port M Wired-Or Mode Register (WOMM).
- Figure 3-22 Port P I/O Register (PTP)
- Figure 3-23 Port P Input Register (PTIP)
- Figure 3-24 Port P Data Direction Register (DDRP)
- Figure 3-25 Port P Reduced Drive Register (RDRP)
- Figure 3-26 Port P Pull Device Enable Register (PERP)
- Figure 3-27 Port P Polarity Select Register (PPSP)
- Figure 3-28 Port P Interrupt Enable Register (PIEP)
- Figure 3-29 Port P Interrupt Flag Register (PIFP).
- Figure 3-30 Port J I/O Register (PTJ)
- Figure 3-31 Port J Input Register (PTIJ)
- Figure 3-32 Port J Data Direction Register (DDRJ)
- Figure 3-33 Port J Reduced Drive Register (RDRJ)
- Figure 3-34 Port J Pull Device Enable Register (PERJ)
- Figure 3-35 Port J Polarity Select Register (PPSJ).
- Figure 3-36 Port J Interrupt Enable Register (PIEJ)
- Figure 3-37 Port J Interrupt Flag Register (PIFJ)
- Figure 3-38 Port AD I/O Register (PTAD)
- Figure 3-39 Port AD Input Register (PTIAD).
- Figure 3-40 Port AD Data Direction Register (DDRAD)
- Figure 3-41 Port AD Reduced Drive Register (RDRAD).
- Figure 3-42 Port AD Pull Device Enable Register (PERAD).
- Figure 3-43 Port AD Polarity Select Register (PPSAD)
- Figure 4-1 Illustration of I/O pin functionality.
- Figure 4-2 Interrupt Glitch Filter on Port P and J (PPS=0)
- Figure 4-3 Pulse Illustration
- Table 2-1 Pin Functions and Priorities List of Tables
- Table 3-1 Module Memory Map
- Table 3-2 Pin Configuration Summary
- Table 3-3 Port T[4:0] Pin Functionality Configurations
- Table 4-1 Pulse Detection Criteria
- Table 5-1 Port Reset State Summary
- Table 6-1 Port Integration Module Interrupt Sources
1.1 Overview
The Port Integration Module establishes the interface between the peripheral modules and the I/O pins for
all ports.
This section covers:
- Port A, B and E related to the core logic and the multiplexed bus interface,
- Port T connected to the TIM module (PWM module can be routed to port T as well),
- Port S connected to the SCI module,
- Port M associated to the MSCAN and SPI module,
- Port P connected to the PWM module, external interrupt sources available
- Port J pins can be used as external interrupt sources and standard I/O’s
The following I/O pin configurations can be selected:
Available on all I/O pins:
- Input/output selection
- Drive strength reduction,
- Enable and select of pull resistors,
Available on all Port P and Port J pins:
- Interrupt enable and status flags
The implementation of the Port Integration Module is device dependent.
A standard port has the following minimum features:
- Input/output selection
- 5V output drive with two selectable drive strength
- 5V digital and analog input
- Input with selectable pull-up or pull-down device
Optional features:
- Open drain for wired-or connections
- Interrupt inputs with glitch filtering
1.2 Features
A standard port has the following minimum features:
- Input/output selection
- 5V output drive with two selectable drive strength
- 5V digital and analog input
- Input with selectable pull-up or pull-down device
Optional features:
- Open drain for wired-or connections
- Interrupt inputs with glitch filtering
Section 2 External Signal Description
2.1 Overview
This section lists and describes the signals that do connect off-chip.
2.2 Signal properties
Table 2-1 shows all pins and their functions that are controlled by the PIM9C32 module. If there is more
than one function associated to a pin, the priority is indicated by the position in the table from top (highest
priority) to down (lowest priority).
Section 3 Memory Map/Register Definition
3.1 Overview
This section provides a detailed description of all registers.
3.2 Module Memory Map
Table 3-1 shows the register map of the Port Integration Module.
Port E
PE
NOACC/
XCLKS/
GPIO
Refer to MEBI in HCS12 Core User Guide.
PE
IPIPE1/
MODB/
GPIO
PE
IPIPE0/
MODA/
GPIO
PE4 ECLK/GPIO
PE
LSTRB/
TAGLO/
GPIO
PE
R/W/
GPIO
PE1 IRQ/GPI
PE0 XIRQ/GPI
Table 3-1 Module Memory Map
Address
offset Use^ Access
$00 Port T I/O Register (PTT) RW $01 Port T Input Register (PTIT) R $02 Port T Data Direction Register (DDRT) RW $03 Port T Reduced Drive Register (RDRT) RW $04 Port T Pull Device Enable Register (PERT) RW $05 Port T Polarity Select Register (PPST) RW $06 Reserved - $07 Port T Module Routing Register (MODRR) (^) RW 1
$08 Port S I/O Register (PTS) (^) RW 1 $09 Port S Input Register (PTIS) R
Port Pin Name Pin Function Description
Pin
Function
after Reset
$0A Port S Data Direction Register (DDRS) (^) RW 1
$0B Port S Reduced Drive Register (RDRS) (^) RW 1 $0C Port S Pull Device Enable Register (PERS) (^) RW 1 $0D Port S Polarity Select Register (PPSS) (^) RW 1
$0E Port S Wired-Or Mode Register (WOMS) (^) RW 1 $0F Reserved - $10 Port M I/O Register (PTM) (^) RW 1 $11 Port M Input Register (PTIM) R $12 Port M Data Direction Register (DDRM) (^) RW 1 $13 Port M Reduced Drive Register (RDRM) (^) RW 1 $14 Port M Pull Device Enable Register (PERM) (^) RW 1
$15 Port M Polarity Select Register (PPSM) (^) RW 1 $16 Port M Wired-Or Mode Register (WOMM) (^) RW 1 $17 Reserved - $18 Port P I/O Register (PTP) RW $19 Port P Input Register (PTIP) R $1A Port P Data Direction Register (DDRP) RW $1B Port P Reduced Drive Register (RDRP) RW $1C Port P Pull Device Enable Register (PERP) RW $1D Port P Polarity Select Register (PPSP) RW $1E Port P Interrupt Enable Register (PIEP) RW $1F Port P Interrupt Flag Register (PIFP) RW $20-$27 Reserved - $28 Port J I/O Register (PTJ) (^) RW 1 $29 Port J Input Register (PTIJ) R $2A Port J Data Direction Register (DDRJ) (^) RW 1 $2B Port J Reduced Drive Register (RDRJ) (^) RW 1
$2C Port J Pull Device Enable Register (PERJ) (^) RW 1 $2D Port J Polarity Select Register (PPSJ) (^) RW 1
$2E Port J Interrupt Enable Register (PIEJ) (^) RW 1 $2F Port J Interrupt Flag Register (PIFJ) (^) RW 1 $30 Port AD I/O Register (PTAD) RW $31 Port AD Input Register (PTIAD) R $32 Port AD Data Direction Register (DDRAD) RW $33 Port AD Reduced Drive Register (RDRAD) RW $34 Port AD Pull Device Enable Register (PERAD) RW $35 Port AD Polarity Select Register (PPSAD) RW $36-$3F Reserved -
NOTES:
- Write access not applicable for one or more register bits. Please refer to detailed signal de- scription.
Table 3-1 Module Memory Map
3.3.1 Port T Registers
Figure 3-1 Port T I/O Register (PTT)
Read:Anytime.
Write:Anytime.
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register,
otherwise the value at the pins is read.
If a TIM-channel is defined as output, the related port T is assigned to IOC function.
In addition to the possible timer functionality of port T pins PWM channels [4:0] can be routed to port
T[4:0]. For this the Module Routing Register (MODRR) needs to be configured.
Table 3-3 Port T[4:0] Pin Functionality Configurations
Address Offset: $__
Bit 7 6 5 4 3 2 1 Bit 0 Read: PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT Write TIM IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC PWM PWM4 PWM3 PWM2 PWM1 PWM Reset: 0 0 0 0 0 0 0 0
= Reserved or unimplemented
MODRR[x] PWME[x] TIMEN[x] Port T[x] output
0 0 0 General Purpose I/O
0 0 1 Timer
0 1 0 General Purpose I/O
0 1 1 Timer
1 0 0 General Purpose I/O
1 0 1 Timer
1 1 0 PWM
1 1 1 PWM
NOTES:
- TIMEN[x] means that the timer is enabled (TSCR1[7]), the related channel is configured for output compare function (TIOS[x] (or special output on a timer overflow event - configurable in TTOV[x][) and the timer output is routed to the port pin (TCTL1 / TCTL2).
- All Fields they are don’t shaded in grey are standard use cases.
Figure 3-2 Port T Input Register (PTIT)
Read:Anytime.
Write:Never, writes to this register have no effect.
This register always reads back the status of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
Figure 3-3 Port T Data Direction Register (DDRT)
Read:Anytime.
Write:Anytime.
This register configures each port T pin as either input or output.
The standard TIM / PWM modules forces the I/O state to be an output for each standard TIM / PWM
module port associated with an enabled output compare. In these cases the data direction bits will not
change.
The DDRT bits revert to controlling the I/O direction of a pin when the associated timer output compare
is disabled.
The timer input capture always monitors the state of the pin.
DDRT[7:0] — Data Direction Port T
1 = Associated pin is configured as output. 0 = Associated pin is configured as input.
Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on
PTT or PTIT registers, when changing the DDRT register.
Address Offset: $__
Bit 7 6 5 4 3 2 1 Bit 0 Read: PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT Write: Reset: - - - - - - - -
= Reserved or unimplemented
Address Offset: $__
Bit 7 6 5 4 3 2 1 Bit 0 Read: DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT Write: Reset: 0 0 0 0 0 0 0 0
= Reserved or unimplemented
Figure 3-6 Port T Polarity Select Register (PPST)
Read:Anytime.
Write:Anytime.
This register selects whether a pull-down or a pull-up device is connected to the pin.
PPST[7:0] — Pull Select Port T
1 = A pull-down device is connected to the associated port T pin, if enabled by the associated bit in register PERT and if the port is used as input. 0 = A pull-up device is connected to the associated port T pin, if enabled by the associated bit in register PERT and if the port is used as input.
Figure 3-7 Port T Module Routing Register (MODRR)
Read:Anytime.
Write:Anytime.
This register selects the module connected to port T.
MODRR[4:0] — Module Routing Register Port T
1 = Associated pin is connected to PWM module 0 = Associated pin is connected to TIM module
Address Offset: $__
Bit 7 6 5 4 3 2 1 Bit 0 Read: PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST Write: Reset: 0 0 0 0 0 0 0 0
= Reserved or unimplemented
Address Offset: $__
Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 MODRR4 MODRR3 MODRR2 MODRR1 MODRR Write: Reset: - - - 0 0 0 0 0
= Reserved or unimplemented
3.3.2 Port S Registers
Figure 3-8 Port S I/O Register (PTS)
Read:Anytime.
Write:Anytime.
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register,
otherwise the value at the pins is read.
The SCI port associated with transmit pin 1 is configured as output if the transmitter is enabled and the
SCI pin associated with receive pin 0 is configured as input if the receiver is enabled. Please refer to SCI
Block User Guide for details.
Figure 3-9 Port S Input Register (PTIS)
Read:Anytime.
Write:Never, writes to this register have no effect.
This register always reads back the status of the associated pins. This also can be used to detect overload
or short circuit conditions on output pins.
Address Offset: $__
Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 PTS3 PTS2 PTS1 PTS Write: SCI - - - - - - TXD RXD Reset: 0 0 0 0 0 0 0 0
= Reserved or unimplemented
Address Offset: $__
Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 PTIS3 PTIS2 PTIS1 PTIS Write: Reset: - - - - - - - -
= Reserved or unimplemented
