embedded systems using MSP430, Exercises of Embedded Systems

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Contents

 (^) MSP430 architecture:  (^) Main characteristics  (^) Architecture topology  (^) Address space  (^) Interrupt vector table  (^) Central Processing Unit (MSP430 CPU)  (^) Central Processing Unit (MSP430X CPU)  (^) Addressing modes  (^) Instructions set  (^) Quiz

Microcontroller characteristics

 (^) Integration: Able to implement a whole design onto a single chip.  (^) Cost: Are usually low-cost devices (a few $ each);  (^) Clock frequency: Compared with other devices (microprocessors and DSPs), MCUs use a low clock frequency:  (^) MCUs today run up to 100 MHz/100 MIPS (Million Instructions Per Second).  (^) Power consumption: Low power (battery operation);  (^) Bits: 4 bits (older devices) to 32 bits devices;  (^) Memory: Limited available memory, usually less than 1 MByte;  (^) Input/Output (I/O): Low to high (8 to 150) pin-out count.

MSP430 main characteristics (1/3)

 (^) Low power consumption:  (^) 0.1 A for RAM data retention;  (^) 0.8 A for real-time clock mode operation;  (^250) A/MIPS during active operation.  (^) Low operation voltage (from 1.8 V to 3.6 V);  (^) < 1 s clock start-up;  (^) < 50 nA port leakage;  (^) Zero-power Brown-Out Reset (BOR).

MSP430 main characteristics (3/3)

 (^) Flexibility:  (^) Up to 256 kByte Flash;  (^) Up to 100 pins;  (^) USART, I2C, Timers;  (^) LCD driver;  (^) Embedded emulation;  (^) And many more peripherals modules…  (^) Microcontroller performance:  (^) Instruction processing on either bits, bytes or words  (^) Reduced instructions set;  (^) Compiler efficient;  (^) Wide range of peripherals;  (^) Flexible clock system.

MSP430 Architecture

 (^) Block diagram:

Interrupt vector table

 (^) Mapped at the very end of memory space (upper 16 words of Flash/ROM): 0FFE0h - 0FFFEh (4xx devices);  (^) Priority of the interrupt vector increases with the word address.

Central Processing Unit (MSP430 CPU) (1/7)

 (^) RISC (Reduced Instructions Set Computing) architecture:  (^) Instructions are reduced to the basic ones (short set):

○ 27 physical instructions;

○ 24 emulated instructions.

 (^) This provides simpler and faster instruction decoding;  (^) Interconnect by a using a common memory address bus (MAB) and memory data bus (MDB) - Von Neumann architecture:

○ Makes use of only one storage structure for data and

instructions sets.

○ The separation of the storage processing unit is

implicit;

○ Instructions are treated as data (programmable).

Central Processing Unit (MSP430 CPU) (3/7)

 (^) Incorporates sixteen 16-bit registers:

○ 4 registers (R0, R1, R2 and R3) have dedicated

functions;

○ 12 register are working registers (R4 to R15) for

general use.

 (^) R0: Program Counter (PC):  (^) Points to the next instruction to be read from memory and executed by the CPU.  (^) R1: Stack Pointer (SP):  (^) 1st: stack can be used by user to store data for later use (instructions: store by PUSH, retrieve by POP);  (^) 2nd: stack can be used by user or by compiler for subroutine parameters (PUSH, POP in calling routine; addressed via offset calculation on stack pointer (SP) in called subroutine);

Central Processing Unit (MSP430 CPU) (4/7)

 (^) R1: Stack Pointer (SP) (continued):  (^) 3rd: used by subroutine calls to store the program counter value for return at subroutine's end (RET);  (^) 4th: used by interrupt - system stores the actual PC value first, then the actual status register content (on top of stack) on return from interrupt (RETI) the system get the same status as just before the interrupt happened (as long as none has changed the value on TOS) and the same program counter value from stack.

Central Processing Unit (MSP430 CPU) (6/7)

 (^) R2/R3: Constant Generator Registers (CG1/CG2):  (^) Depending of the source-register addressing modes (As) value, six constants can be generated without code word or code memory access to retrieve them.  (^) This is a very powerful feature which allows the implementation of emulated instructions, for example, instead of implement a core instruction for an increment the constant generator is used. 16 Register As Constant Remarks R2 00 - (^) Register mode R2 01 (0) (^) Absolute mode R2 10 00004h +4, bit processing R2 11 00008h (^) +8, bit processing R3 00 00000h (^) 0, word processing R3 01 00001h + R3 10 00002h +2, bit processing R3 11 0FFFFh -1, word processing

Central Processing Unit (MSP430 CPU) (7/7)

 (^) R4 - R15: General–Purpose Registers:  (^) These general-purpose registers are adequate to store data registers, address pointers, or index values and can be accessed with byte or word instructions. 17

Central Processing Unit (MSP430X CPU) (2/10)

 (^) Organization of the MSP430X CPU:  (^) Although the MSP430X CPU structure is similar to that of the MSP430 CPU, there are some differences that will now be highlighted;  (^) With the exception of the status register SR, all MSP430X registers are 20 bits;  (^) The CPU can now process 20-bit or 16-bit data.

Central Processing Unit (MSP430X CPU) (3/10)

 (^) The MSP430X CPU has 16 registers, some of which have special use:  (^) R0 (PC) Program Counter:  (^) Has the same function as the MSP430 CPU, although now it has 20 bits.  (^) R1 (SP) Stack Pointer:  (^) Has the same function as the MSP430 CPU, although now it has 20 bits.  (^) R2 (SR) Status Register:  (^) Has the same function as the MSP430 CPU, but it still has 16 bits.