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The instructions and problems for the ece 2030 d computer engineering exam held in spring 2012. The exam consists of 4 problems, each with multiple parts, totaling 100 points. The problems cover various topics such as incomplete circuits, boolean algebra, karnaugh maps, and mixed logic design.
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4 problems, 5 pages Exam One 9 February 2012 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate the pages of the exam. For maximum credit, show your work. Good Luck! Your Name ( please print ) ________________________________________________ 1 2 3 4 total 30 20 24 26 100
4 problems, 5 pages Exam One 9 February 2012 Problem 1 (3 parts, 30 points) Incomplete Circuits The three parts below contain (A) a pull up network, (B) a pull down network, and (C) an expression to be implemented. For (A) and (B), complete the missing complementary switching networks so the circuit contains no floats or shorts and write the Boolean expression computed by the completed circuit. For (C), design the entire switching network. Assume the inputs and their complements are available. OUTx = OUTy = OUTz = A โ (^ D + B โ C^ )
4 problems, 5 pages Exam One 9 February 2012 Problem 3 (2 parts, 24 points) Karnaugh Maps Part A (12 points) For the following expression, derive a simplified sum of products expression using a Karnaugh Map. Circle and list all prime implicants, indicating which are essential. Out =( A + C + D )โ ( A + B + D )โ ( A + B + C )โ ( A + B + D ) simplified SOP expression Part B (12 points) For the following expression, derive a simplified product of sums expression using a Karnaugh Map. Circle and list all prime implicants, indicating which are essential. Out = B โ C โ D + A โ B โ D + B โ C โ D + B โ C โ D simplified POS expression
4 problems, 5 pages Exam One 9 February 2012 Problem 4 (2 parts, 26 points) Mixed Logic Design Part A (12 points) The following design has no supporting documentation. Derive the desired Boolean expression and the implementation cost (in CMOS transistors). Do not simplify the expressions. OUTX = OUTY =
Part B (14 points) Now reimplement these expressions using NAND gates and inverters. Use proper mixed logic notation. Determine the cost of this implementation (in transistors).
