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The instructions and problems for an introduction to computer engineering exam held on february 2, 2007. The exam covers topics such as binary and decimal conversions, logic functions, and switch networks. Students are required to solve conversion problems, complete truth tables, and design logic circuits.
Typology: Exams
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February 2, 2007 Page 1 of 5
Name:
Student Number:
DO NOT WRITE IN THIS BOX SIGNATURE
Problem 1. (16 points possible)
Problem 2. (10 points possible)
Problem 3. (14 points possible)
Problem 4. (10 points possible)
TOTAL. (50 points possible)
February 2, 2007 Page 2 of 5
Problem 1. (16 points)
A. (7 points) Perform each of the following conversions. Write your answers in the boxes at the right edge.
(i) Convert 1001011012 to decimal.
(ii) Convert 18210 to binary.
(iii) Convert 100111012 to octal.
(iv) Convert 6378 to decimal.
(v) Convert 6D9 16 to binary.
(vi) Convert 70310 to hexadecimal.
(vii) Convert B5D9 16 to octal.
B. (9 points) In the blank in front of each expression in the left hand column, write the letter (P – Z) corresponding to the equivalent expression in the right hand column. Not all answers in the right hand column will be used and some may be used more than once.
(i) _____ (A + B) (A + C) (B + C) P) A B C + A B C
(ii) _____ (A + C + D) (B + C D) R) A C + A B D + A B D
(iii) _____ A + C + B + (D + A) T) A C + A B D
Z) None of the above
February 2, 2007 Page 4 of 5
Problem 3. (14 points)
A. (6 points) A CMOS switch network is shown below. Write the connectivity functions for
the pull-up and pull-down networks, FPU and FPD. Complete the truth table for this network, specifying the circuit output as “0,” “1,” “float,” or “short” for each input combination.
C
B A
C
B
C A
F
B. (8 points) Complete each of the switch-logic diagrams below by constructing the missing network as the dual of the pull-up or pull-down network given. Write the logic expression for the function implemented by each switch network.
T
T
S
R
J
Y X
Z Y
G
February 2, 2007 Page 5 of 5
Problem 4. (10 points)
A. (4 points) A schematic is given below for a circuit implemented using only NAND gates and INVERTERs. Add complement bars to the diagram to make it a valid mixed-logic schematic. Then, write an algebraic expression for the function this mixed-logic circuit implements. Your expression should correspond to the circuit structure given; do not attempt to algebraically minimize the expression.
F
D E
C
B
A
B. (6 points) Draw a mixed-logic schematic to implement the function from part A using only physical NOR gates and INVERTERs. Your schematic should correspond to the expression from part A; do not attempt to minimize or otherwise algebraically manipulate the expression. You should make a reasonable effort to minimize the number of inverters required. Then, determine the number of each type of physical logic gate that would be required to implement this circuit as drawn.
# of gates: ____ NOR ____ INVERTER